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Re: [Qemu-devel] [Qemu-arm] [PATCH] hw/arm/bcm2836: Wire up CPU timer in
Re: [Qemu-devel] [Qemu-arm] [PATCH] hw/arm/bcm2836: Wire up CPU timer interrupts correctly
Thu, 17 Mar 2016 07:54:56 -0600
On 17 March 2016 at 07:46, Peter Maydell <address@hidden> wrote:
> On 17 March 2016 at 13:37, Thomas Hanson <address@hidden> wrote:
>> On Mar 17, 2016 4:33 AM, "Peter Maydell" <address@hidden> wrote:
>>> Wire up the CPU timer interrupts in the right order, with the
>>> nonsecure physical timer on cntpnsirq, the hyp timer on cnthpirq,
>>> and the secure physical timer on cntpsirq. (We did get the
>>> virt timer right, at least.)
>> What drives the order?
> This is modelling the hardware:
> The interrupt controller has 4 lines named CNTPSIRQ, CNTPNSIRQ, etc,
> and we need to hook the lines from the CPU up to the interrupt
> controller appropriately. The names we ended up with in QEMU's
> CPU model (GTIMER_PHYS, etc) don't match the signal names that
> a hardware A7 uses, which is slightly irritating, but not a big deal.
> The A7 TRM lists which timer is which signal:
> (though you can pretty much guess from the signal names).
> -- PMM
Ah, thanks. I was thinking time-order. It's still early...