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[Qemu-devel] [PULL for-2.6] tcg/mips: Fix type of tcg_target_reg_alloc_o

From: Richard Henderson
Subject: [Qemu-devel] [PULL for-2.6] tcg/mips: Fix type of tcg_target_reg_alloc_order[]
Date: Tue, 5 Apr 2016 12:51:20 -0700

From: James Hogan <address@hidden>

The MIPS TCG backend is the only one to have
tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base
temporaries in a different order") breaking the build on MIPS since the
type differed from indirect_reg_alloc_order[]:

tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression 
     order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;

Make it an array of ints to fix the build and match other architectures.

Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different 
Signed-off-by: James Hogan <address@hidden>
Acked-by: Aurelien Jarno <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
 tcg/mips/tcg-target.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 297bd00..682e198 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -76,7 +76,7 @@ static const char * const 
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 #define TCG_TMP1  TCG_REG_T9
 /* check if we really need so many registers :P */
-static const TCGReg tcg_target_reg_alloc_order[] = {
+static const int tcg_target_reg_alloc_order[] = {
     /* Call saved registers.  */

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