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Re: [Qemu-devel] best way to implement emulation of AArch64 tagged addre

From: Tom Hanson
Subject: Re: [Qemu-devel] best way to implement emulation of AArch64 tagged addresses
Date: Fri, 08 Apr 2016 11:20:06 -0600

On Mon, 2016-04-04 at 10:56 -0700, Richard Henderson wrote:
> On 04/04/2016 09:31 AM, Peter Maydell wrote:
> > On 4 April 2016 at 17:28, Richard Henderson <address@hidden> wrote:
> >> On 04/04/2016 08:51 AM, Peter Maydell wrote:
> >>> In particular I think if you just do the relevant handling of the tag
> >>> bits in target-arm's get_phys_addr() and its subroutines then this
> >>> should work ok, with the exceptions that:
> >>>    * the QEMU TLB code will think that [tag A + address X] and
> >>>      [tag B + address X] are different virtual addresses and they will
> >>>      miss each other in the TLB
> >>
> >>
> >> Yep.  Not only miss, but actively contend with each other.
> >
> > Yes. Can we avoid that, or do we just have to live with it? I guess
> > if the TCG fast path is doing a compare on full insn+tag then we
> > pretty much have to live with it.
> We have to live with it.  Implementing a more complex hashing algorithm in 
> the 
> fast path is probably a non-starter.
> Hopefully if one is using multiple tags, they'll still be in the victim cache 
> and so you won't have to fall back to the full tlb lookup.
> r~

It seems like the "best" solution would be to mask the tag in the TLB
and it feels like it should be possible.  BUT I need to dig into the
code more.

Is it an option to mask off the tag bits in all cases? Is there any case
it which those bits are valid address bits?


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