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Re: [Qemu-devel] [PATCH v5 10/18] intel_iommu: Add support for PCI MSI r

From: Jan Kiszka
Subject: Re: [Qemu-devel] [PATCH v5 10/18] intel_iommu: Add support for PCI MSI remap
Date: Thu, 28 Apr 2016 09:32:17 +0200
User-agent: Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv: Gecko/20080226 SUSE/ Thunderbird/ Mnenhy/

On 2016-04-28 09:05, Peter Xu wrote:
> This patch enables interrupt remapping for PCI devices.
> To play the trick, one memory region "iommu_ir" is added as child region
> of the original iommu memory region, covering range 0xfeeXXXXX (which is
> the address range for APIC). All the writes to this range will be taken
> as MSI, and translation is carried out only when IR is enabled.
> Idea suggested by Paolo Bonzini.

This still lacks source (device ID) identification, right? Were did the
memory write attribute thing go? Given that you actually introduce a
separate MSI target address space for the IOAPIC (btw, once there will
be more than one instance, like on real hw today) and that you will need
yet another one for each HPET, why not address this with a common scheme
now, ie. by transmitting the source ID along the write via that attribute?


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