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[Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags |
Date: |
Wed, 4 May 2016 22:12:05 +0200 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 56 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index cc8a000..58cc9d9 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -456,18 +456,66 @@ static TCGv gen_lea_indexed(CPUM68KState *env,
DisasContext *s, TCGv base)
static void gen_flush_flags(DisasContext *s)
{
- TCGv tmp;
+ TCGv t0, t1;
switch (s->cc_op) {
case CC_OP_FLAGS:
return;
+
+ case CC_OP_ADD:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for addition. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_SUB:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_CMP:
+ tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
+ tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
+ break;
+
+ case CC_OP_LOGIC:
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ break;
+
case CC_OP_DYNAMIC:
gen_helper_flush_flags(cpu_env, QREG_CC_OP);
break;
+
default:
- tmp = tcg_const_i32(s->cc_op);
- gen_helper_flush_flags(cpu_env, tmp);
- tcg_temp_free(tmp);
+ t0 = tcg_const_i32(s->cc_op);
+ gen_helper_flush_flags(cpu_env, t0);
+ tcg_temp_free(t0);
break;
}
--
2.5.5
- Re: [Qemu-devel] [PATCH 18/52] target-m68k: Some fixes to SR and flags management, (continued)
- [Qemu-devel] [PATCH 20/52] target-m68k: Remove incorrect clearing of cc_x, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 19/52] target-m68k: terminate cpu dump with newline, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 22/52] target-m68k: Introduce DisasCompare, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 21/52] target-m68k: Reorg flags handling, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 24/52] target-m68k: Optimize some comparisons, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags,
Laurent Vivier <=
- [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 27/52] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 28/52] target-m68k: add addx/subx/negx ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 29/52] target-m68k: factorize flags computing, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 30/52] target-m68k: add scc/dbcc, Laurent Vivier, 2016/05/04