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[Qemu-devel] [PATCH v4 0/1] arm: Steps towards EL2 support round 6

From: Edgar E. Iglesias
Subject: [Qemu-devel] [PATCH v4 0/1] arm: Steps towards EL2 support round 6
Date: Thu, 5 May 2016 18:10:00 +0200

From: "Edgar E. Iglesias" <address@hidden>


Another round of patches towards EL2 support. This one adds partial
Instruction Syndrome generation for Data Aborts while running in AArch64.

I don't feel very confident with the way I collect the regsize info used
to fill out the SF field. Feedback on that would be great.

Once we sort out the details on how this should be implemented we can
fill out the parts needed for AArch32. Possibly in a future version of
this same series.

Comments welcome!

Best regards,

ChangeLog v3 -> v4
* Assert that we only set the syndrome template once per insn
* Mask out upper six bits from syndrome template
* Remove the _with_isv versions of do_gpr_ld/st
* Mention that we only handle AArch64 in the commit message

v2 -> v3:
* Commented on inst start extra words
* Add macro for word2 shift
* Move ISS field collection closer to tcg_gen_qemu_ld/st
* Changed logic to compute regsize for disas_ld_lit
* Introduce syn_data_abort_with_iss/no_iss
* Rename some isv naming to iss
* Drop the patch: "Use isyn.swstep.ex to hold the is_ldex state"

v1 -> v2:
* Reworked the syndrome generation code to reuse syn_data_abort for
  the encoding.
* Reworded a bunch of comments.
* Fixed thumb vs 16bit IL field issue.

Edgar E. Iglesias (1):
  target-arm: A64: Create Instruction Syndromes for Data Aborts

 target-arm/cpu.h           |  14 ++++-
 target-arm/op_helper.c     |  49 ++++++++++++++--
 target-arm/translate-a64.c | 140 ++++++++++++++++++++++++++++++++++++++-------
 target-arm/translate.c     |   5 +-
 target-arm/translate.h     |   2 +
 5 files changed, 180 insertions(+), 30 deletions(-)


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