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Re: [Qemu-devel] [PATCH 4/4] kvm: support MSI_X2APIC capability

From: Radim Krčmář
Subject: Re: [Qemu-devel] [PATCH 4/4] kvm: support MSI_X2APIC capability
Date: Mon, 9 May 2016 17:08:28 +0200

2016-05-07 16:03+0200, Jan Kiszka:
> On 2016-05-06 22:53, Radim Krčmář wrote:
>> The capability alows us to express x2APIC destinations.
> "allows"

Thanks. :)

> Will the possibility to create >254 CPUs be indirectly coupled to this
> capability, or should userland check for it explicitly then?

Yes, for now, so I would prefer if userspace checked explicitly.
Greater amount of VCPUs needs to be checked with KVM_CAP_MAX_VCPUS, but
it's not guaranteed that all kernels with maximum above 255 will have
KVM_CAP_MSI_X2APIC as there are other methods of sending an interrupt.

> Will the kernel handle the case gracefully that AMD CPUs will report the
> capability as well, although there is no x2APIC (at least so far) with
> those CPU types, and we still inject MSI messages with that flag set
> (just to double-check if the case was thought through)?

Yes, it's perfectly backward compatible.  We allowed x2APIC on emulated
AMD cpus in the past and this just extends the address space to 32 bits.
Maybe the capability should be called MSI_EXTENDED?

(I though about using the same GSI type and just using those upper bits
 + notifiing QEMU with a capability, but userspace could have passed
 garbage in those bits, so it had non-zero risk.)

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