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[Qemu-devel] [PATCH v7 09/25] x86-iommu: provide x86_iommu_get_default
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v7 09/25] x86-iommu: provide x86_iommu_get_default |
Date: |
Tue, 17 May 2016 15:15:37 +0800 |
Instead of searching the device tree every time, one static variable is
declared for the default system x86 IOMMU device. Also, some VT-d
macros are replaced by x86 ones.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/acpi-build.c | 9 ++-------
hw/i386/intel_iommu.c | 8 +++++---
hw/i386/x86-iommu.c | 16 ++++++++++++++++
hw/pci-host/q35.c | 2 +-
include/hw/i386/intel_iommu.h | 1 -
include/hw/i386/x86-iommu.h | 9 +++++++++
6 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6c572a3..9af1da0 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -51,7 +51,7 @@
#include "hw/i386/ich9.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/q35.h"
-#include "hw/i386/intel_iommu.h"
+#include "hw/i386/x86-iommu.h"
#include "hw/timer/hpet.h"
#include "hw/acpi/aml-build.h"
@@ -2656,12 +2656,7 @@ static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
static bool acpi_has_iommu(void)
{
- bool ambiguous;
- Object *intel_iommu;
-
- intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
- &ambiguous);
- return intel_iommu && !ambiguous;
+ return !!x86_iommu_get_default();
}
static
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0a70577..0c7b24d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -25,6 +25,7 @@
#include "intel_iommu_internal.h"
#include "hw/pci/pci.h"
#include "hw/boards.h"
+#include "hw/i386/x86-iommu.h"
/*#define DEBUG_INTEL_IOMMU*/
#ifdef DEBUG_INTEL_IOMMU
@@ -191,7 +192,7 @@ static void vtd_reset_context_cache(IntelIOMMUState *s)
VTD_DPRINTF(CACHE, "global context_cache_gen=1");
while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
- for (devfn_it = 0; devfn_it < VTD_PCI_DEVFN_MAX; ++devfn_it) {
+ for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
vtd_as = vtd_bus->dev_as[devfn_it];
if (!vtd_as) {
continue;
@@ -976,7 +977,7 @@ static void vtd_context_device_invalidate(IntelIOMMUState
*s,
vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
if (vtd_bus) {
devfn = VTD_SID_TO_DEVFN(source_id);
- for (devfn_it = 0; devfn_it < VTD_PCI_DEVFN_MAX; ++devfn_it) {
+ for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
vtd_as = vtd_bus->dev_as[devfn_it];
if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
@@ -1978,7 +1979,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,
PCIBus *bus, int devfn)
if (!vtd_bus) {
/* No corresponding free() */
- vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) *
VTD_PCI_DEVFN_MAX);
+ vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
+ X86_IOMMU_PCI_DEVFN_MAX);
vtd_bus->bus = bus;
key = (uintptr_t)bus;
g_hash_table_insert(s->vtd_as_by_busptr, &key, vtd_bus);
diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c
index d739afb..2d6d221 100644
--- a/hw/i386/x86-iommu.c
+++ b/hw/i386/x86-iommu.c
@@ -22,12 +22,28 @@
#include "hw/boards.h"
#include "hw/i386/x86-iommu.h"
+/* Default X86 IOMMU device */
+static X86IOMMUState *x86_iommu_default = NULL;
+
+static void x86_iommu_set_default(X86IOMMUState *x86_iommu)
+{
+ assert(x86_iommu);
+ assert(x86_iommu_default == NULL);
+ x86_iommu_default = x86_iommu;
+}
+
+X86IOMMUState *x86_iommu_get_default(void)
+{
+ return x86_iommu_default;
+}
+
static void x86_iommu_realize(DeviceState *dev, Error **errp)
{
X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev);
if (x86_class->realize) {
x86_class->realize(dev, errp);
}
+ x86_iommu_set_default(X86_IOMMU_DEVICE(dev));
}
static void x86_iommu_class_init(ObjectClass *klass, void *data)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 70f897e..27ee0c8 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -429,7 +429,7 @@ static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void
*opaque, int devfn)
IntelIOMMUState *s = opaque;
VTDAddressSpace *vtd_as;
- assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
+ assert(0 <= devfn && devfn <= X86_IOMMU_PCI_DEVFN_MAX);
vtd_as = vtd_find_add_as(s, bus, devfn);
return &vtd_as->as;
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index c88a931..04265ca 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -35,7 +35,6 @@
#define VTD_PCI_BUS_MAX 256
#define VTD_PCI_SLOT_MAX 32
#define VTD_PCI_FUNC_MAX 8
-#define VTD_PCI_DEVFN_MAX 256
#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
index 924f39a..d6991cb 100644
--- a/include/hw/i386/x86-iommu.h
+++ b/include/hw/i386/x86-iommu.h
@@ -30,6 +30,9 @@
#define X86_IOMMU_GET_CLASS(obj) \
OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
+#define X86_IOMMU_PCI_DEVFN_MAX 256
+#define X86_IOMMU_SID_INVALID (0xffff)
+
typedef struct X86IOMMUState X86IOMMUState;
typedef struct X86IOMMUClass X86IOMMUClass;
@@ -43,4 +46,10 @@ struct X86IOMMUState {
SysBusDevice busdev;
};
+/**
+ * x86_iommu_get_default - get default IOMMU device
+ * @return: pointer to default IOMMU device
+ */
+X86IOMMUState *x86_iommu_get_default(void);
+
#endif
--
2.4.11
- [Qemu-devel] [PATCH v7 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 01/25] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 03/25] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 02/25] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 05/25] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 04/25] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 06/25] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 10/25] x86-iommu: q35: generalize find_add_as(), Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 09/25] x86-iommu: provide x86_iommu_get_default,
Peter Xu <=
- [Qemu-devel] [PATCH v7 11/25] intel_iommu: add IR translation faults defines, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 12/25] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 13/25] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 14/25] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 15/25] intel_iommu: add support for split irqchip, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 17/25] x86-iommu: introduce IEC notifiers, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 16/25] q35: add "intremap" parameter to enable IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 19/25] intel_iommu: Add support for Extended Interrupt Mode, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 20/25] intel_iommu: add SID validation for IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 18/25] ioapic: register IOMMU IEC notifier for ioapic, Peter Xu, 2016/05/17