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Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI h

From: Marcel Apfelbaum
Subject: Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI hotplug
Date: Wed, 18 May 2016 17:52:29 +0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0

On 05/18/2016 05:42 PM, Michael S. Tsirkin wrote:
On Wed, May 18, 2016 at 04:31:46PM +0200, Igor Mammedov wrote:
On Wed, 18 May 2016 17:12:09 +0300
Marcel Apfelbaum <address@hidden> wrote:

On 05/18/2016 05:11 PM, Michael S. Tsirkin wrote:
On Wed, May 18, 2016 at 03:59:29PM +0200, Igor Mammedov wrote:
On Sun, 15 May 2016 22:23:32 +0300
Marcel Apfelbaum <address@hidden> wrote:

Using the firmware assigned MMIO ranges for 64-bit PCI window
leads to zero space for hot-plugging PCI devices over 4G.

PC machines can use the whole CPU addressable range after
the space reserved for memory-hotplug.

Signed-off-by: Marcel Apfelbaum <address@hidden>
that patch also has side effect of unconditionally adding
QWordMemory() resource in PCI0._CRS
on all machine types with QEMU generated ACPI tables.

Have you tested that it won't break boot of legacy OSes
(XP, WS2003, old linux with 32bit kernel)?

It's almost sure it break it.
Maybe you can check _REV in _CRS to work around this for XP.

I'll try it.
but only after you check if just presence of QWord would crash XP,
so in case it doesn't crash we would keep _CRS simple static

I very vaguely recall that XP ignored QWord in PCI0._CRS,
but it was long time ago so it won't hurt to recheck.

I played with different guests (32 and 64 bit)
at some point.

Generally, windows tends to crash when CRS resources exceed the
supported limits
of physical memory (sometimes with weird off by one errors,
e.g. win7 32 bit seems to survive with a 36 bit pci hole even though
this means the max address is 2^37-1 which it can't address).

This might depend on CPU as well.

It seems QEMU returns 40-bit as CPU addressable bits, but I might got it wrong.

Which makes me ask: why don't we fix this in BIOS?
If you want it to allocate a large window, do it.

I don't follow, BIOS can assign resources to PCI devices, but how to
specify a MMIO range for hot-plug? Add it to the CRS of the host-bridge, right?



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