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Re: [Qemu-devel] [PATCH] target-s390x: Mask the SIGP order_code to 8bit.
From: |
Philipp Kern |
Subject: |
Re: [Qemu-devel] [PATCH] target-s390x: Mask the SIGP order_code to 8bit. |
Date: |
Sun, 29 May 2016 16:10:35 +0200 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
Hi,
On Wed, Aug 26, 2015 at 11:18:42AM +0200, Alexander Graf wrote:
> On 20.08.15 19:16, Thomas Huth wrote:
> > On 18/08/15 04:50, Philipp Kern wrote:
> >> According to "CPU Signaling and Response", "Signal-Processor Orders",
> >> the order field is bit position 56-63. Without this, the Linux
> >> guest kernel is sometimes unable to stop emulation and enters
> >> an infinite loop of "XXX unknown sigp: 0xffffffff00000005".
> >>
> >> Signed-off-by: Philipp Kern <address@hidden>
> >> ---
> >> target-s390x/misc_helper.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> >> index 8eac0e1..0f0907c 100644
> >> --- a/target-s390x/misc_helper.c
> >> +++ b/target-s390x/misc_helper.c
> >> @@ -500,7 +500,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t
> >> order_code, uint32_t r1,
> >> /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered
> >> register"
> >> as parameter (input). Status (output) is always R1. */
> >>
> >> - switch (order_code) {
> >> + switch (order_code & 0xff) {
> >> case SIGP_SET_ARCH:
> >> /* switch arch */
> >> break;
> >
> > Reviewed-by: Thomas Huth <address@hidden>
> Thanks, applied to s390-next.
it looks like this patch never made it to qemu master. Could someone apply it
please?
(It also seems to be the only pending patch in agraf's s390-next[1].)
Kind regards and thanks
Philipp Kern
[1] https://github.com/agraf/qemu/tree/s390-next
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