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Re: [Qemu-devel] [RFC PATCH v1 1/2] target-arm: Update page size for aar

From: Vijay Kilari
Subject: Re: [Qemu-devel] [RFC PATCH v1 1/2] target-arm: Update page size for aarch64
Date: Tue, 31 May 2016 14:34:59 +0530

Hi Peter

On Wed, Apr 6, 2016 at 8:31 PM, Vijay Kilari <address@hidden> wrote:
> On Mon, Apr 4, 2016 at 10:14 PM, Peter Maydell <address@hidden> wrote:
>> On 4 April 2016 at 17:40, Vijay Kilari <address@hidden> wrote:
>>> On Mon, Apr 4, 2016 at 7:14 PM, Peter Maydell <address@hidden> wrote:
>>>> I agree that this would definitely improve performance (both for
>>>> migration and for emulated guests), but I'm afraid this breaks
>>>> running 32-bit ARMv5 and ARMv7M guests with this QEMU binary,
>>>> so we can't do this. If we want to allow the minimum page size to
>>>> be bigger than 1K for AArch64 CPUs then we need to make it a
>>>> runtime settable thing rather than compile-time (which is not
>>>> an entirely trivial thing).
>>> Do you mean to say that based on -cpu type qemu option
>>> choose the page size at runtime?
>> If you want to avoid defining TARGET_PAGE_SIZE to the
>> lowest-common-denominator 1K, then yes, you'd need to
>> choose it at runtime. That could be painful to implement.
> Had a look at it. Needs some changes in common code as well.
> I will send this as a separate patch series and drop this patch
> from this series.

The L1 page table size, L1 shift are dependent on TARGET_PAGE_BITS(page size).
as shown in snippet code below from translate-all.c

/* The bits remaining after N lower levels of page tables.  */
#define V_L1_BITS_REM \

#if V_L1_BITS_REM < 4
#define V_L1_BITS  (V_L1_BITS_REM + V_L2_BITS)
#define V_L1_BITS  V_L1_BITS_REM

#define V_L1_SIZE  ((target_ulong)1 << V_L1_BITS)


/* The bottom level has pointers to PageDesc */
static void *l1_map[V_L1_SIZE];

How about adding CONFIG_PAGE_SIZE option to configure?.

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