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Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

From: Benjamin Herrenschmidt
Subject: Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode
Date: Mon, 06 Jun 2016 13:55:33 +1000

On Mon, 2016-06-06 at 11:17 +1000, David Gibson wrote:
> On Fri, Jun 03, 2016 at 02:11:17PM +0200, Cédric Le Goater wrote:
> > 
> > This is follow up to complete the serie "ppc: preparing pnv landing
> > (round 2)" plus a little fix on instruction privileges.
> > 
> > Tested on a POWER8 pserie guest and on mac99.
> > 
> > Benjamin Herrenschmidt (2):
> >   ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
> >   ppc: Better figure out if processor has HV mode
> > 
> > Cédric Le Goater (1):
> >   ppc: fix hrfid, tlbia and slbia privilege
> I've applied this series to ppc-for-2.7, swapping the order of patches
> 1 & 2 as Marc requested.  I've also applied the extra patch to fix tlb
> flushing on 32-bit cpus.  I aim to send a pull request once I've done
> my usual tests.
I'm not sure that 32-bit patch is correct. We shouldn't have to flush
on IR/DR transitions at all, that's the whole point of the split I/D

I think something else is wrong.


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