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[Qemu-devel] [PULL 00/26] ppc-for-2.7 queue 20160607


From: David Gibson
Subject: [Qemu-devel] [PULL 00/26] ppc-for-2.7 queue 20160607
Date: Tue, 7 Jun 2016 20:47:47 +1000

The following changes since commit 76462405809d29bab65a3699686998ba124ab942:

  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20160606-1' into staging (2016-06-06 
17:02:42 +0100)

are available in the git repository at:

  git://github.com/dgibson/qemu.git tags/ppc-for-2.7-20160607

for you to fetch changes up to 4d6a0680fa425230748a2d91d81be9afe050eeb3:

  ppc: Do not take exceptions on unknown SPRs in privileged mode (2016-06-07 
13:10:45 +1000)

----------------------------------------------------------------
ppc patch queue for 2016-05-31

Latest patch queue for ppc.  Several significant things in here:
  * A bunch of patches from BenH fixing things in TCG
     - This should fix several regressions introduced by recent
       patches for better HV mode support
     - It also fixes some other bugs discovered along the way
  * Some fixes and cleanups for Mac machine types from Marc
    Cave-Ayland
  * Preliminary patches towards dynamic DMA window support from Alexey
    Kardashevskiy
      - This includes a patch to migration code code
  * Increase number of hotpluggable memory slots
      - Includes a change to KVM generic code, ACKed by Paolo
  * Another TCG fix for an SPE instruction

----------------------------------------------------------------
Alexey Kardashevskiy (6):
      vmstate: Define VARRAY with VMS_ALLOC
      spapr_iommu: Introduce "enabled" state for TCE table
      spapr_iommu: Migrate full state
      spapr_iommu: Add root memory region
      spapr_pci: Reset DMA config on PHB reset
      spapr_pci: Add and export DMA resetting helper

Benjamin Herrenschmidt (11):
      ppc: Better figure out if processor has HV mode
      ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
      ppc: Properly tag the translation cache based on MMU mode
      ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors
      ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode
      ppc: POWER7 had ACOP and PID registers
      ppc: POWER7 has lq/stq instructions and stq need to check ISA
      ppc: Fix mtmsr decoding
      ppc: Fix slbia decode
      ppc: Add missing slbfee. instruction on ppc64 BookS processors
      ppc: Do not take exceptions on unknown SPRs in privileged mode

Bharata B Rao (3):
      kvm: API to obtain max supported mem slots
      spapr: Increase hotpluggable memory slots to 256
      spapr: Introduce pseries-2.7 machine type

C├ędric Le Goater (1):
      ppc: fix hrfid, tlbia and slbia privilege

Mark Cave-Ayland (3):
      target-ppc: fixup bitrot in mmu_helper.c debug statements
      macio: use DMA memory interface for non-block ATAPI transfers
      dbdma: use DMA memory interface for memory accesses

Markus Armbruster (1):
      spapr_pci: Drop cannot_instantiate_with_device_add_yet=false

Talha Imran (1):
      target-ppc/fpu_helper: Fix efscmp* instructions handling

 hw/ide/macio.c              |   3 +-
 hw/misc/macio/mac_dbdma.c   |  13 ++--
 hw/ppc/spapr.c              |  36 ++++++++++--
 hw/ppc/spapr_iommu.c        | 140 +++++++++++++++++++++++++++++++++++---------
 hw/ppc/spapr_pci.c          |  28 ++++++---
 hw/ppc/spapr_vio.c          |   8 +--
 include/hw/pci-host/spapr.h |   2 +
 include/hw/ppc/spapr.h      |  14 +++--
 include/migration/vmstate.h |  10 ++++
 include/sysemu/kvm.h        |   1 +
 kvm-all.c                   |   7 +++
 target-ppc/cpu.h            |   6 +-
 target-ppc/excp_helper.c    |   8 ++-
 target-ppc/fpu_helper.c     |   2 +-
 target-ppc/helper.h         |   1 +
 target-ppc/helper_regs.h    |   8 +--
 target-ppc/mmu-hash64.c     |  30 ++++++++++
 target-ppc/mmu_helper.c     |  74 ++++++++++-------------
 target-ppc/translate.c      |  83 +++++++++++++++++++++-----
 target-ppc/translate_init.c |  39 ++++++++++--
 trace-events                |   2 +
 21 files changed, 388 insertions(+), 127 deletions(-)



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