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Re: [Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set
From: |
Shannon Zhao |
Subject: |
Re: [Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq() |
Date: |
Mon, 13 Jun 2016 15:49:56 +0800 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 |
On 2016/5/26 22:55, Peter Maydell wrote:
> Implement the code which updates the GIC state when an interrupt
> input into the GIC is asserted.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> hw/intc/arm_gicv3.c | 20 +++++++++++++++++++-
> hw/intc/arm_gicv3_dist.c | 21 +++++++++++++++++++++
> hw/intc/arm_gicv3_redist.c | 21 +++++++++++++++++++++
> hw/intc/gicv3_internal.h | 2 ++
> trace-events | 2 ++
> 5 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
> index e8f6766..e770409 100644
> --- a/hw/intc/arm_gicv3.c
> +++ b/hw/intc/arm_gicv3.c
> @@ -311,7 +311,25 @@ static void gicv3_set_irq(void *opaque, int irq, int
> level)
> * [N+32..N+63] : PPI (internal interrupts for CPU 1
> * ...
> */
> - /* Do nothing for now */
> + GICv3State *s = opaque;
> +
> + if (irq < (s->num_irq - GIC_INTERNAL)) {
> + /* external interrupt (SPI) */
> + gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
> + } else {
> + /* per-cpu interrupt (PPI) */
> + int cpu;
> +
> + irq -= (s->num_irq - GIC_INTERNAL);
> + cpu = irq / GIC_INTERNAL;
> + irq %= GIC_INTERNAL;
> + assert(cpu < s->num_cpu);
> + /* Raising SGIs via this function would be a bug in how the board
> + * model wires up interrupts.
> + */
> + assert(irq >= 16 && irq < 32);
Nit: Use GIC_NR_SGIS instead and irq < 32 is unnecessary.
Reviewed-by: Shannon Zhao <address@hidden>
--
Shannon
- Re: [Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq(),
Shannon Zhao <=