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Re: [Qemu-devel] [PATCH 03/10] ppc: Rework POWER7 & POWER8 exception mod

From: Benjamin Herrenschmidt
Subject: Re: [Qemu-devel] [PATCH 03/10] ppc: Rework POWER7 & POWER8 exception model (part 2)
Date: Wed, 15 Jun 2016 07:19:39 +1000

On Tue, 2016-06-14 at 16:25 +1000, David Gibson wrote:
> > Properly implement LPES0/1 handling for HV vs. !HV mode.
> > Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> > [clg: AIL implementation was fixed in commit 5c94b2a5e5ef
> >       fixed checkpatch.pl errors ]
> Code looks ok, but the short description really needs an update,
> since
> this has been taken out of its original series context.

This is still what this does. It properly implements support for LPCR0
(LPCR1 isn't supported). It also fixes how the HV bit is handled when
taking interrupts and which set of SRR's are used in some cases.


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