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Re: [Qemu-devel] [Bug 1594069] Re: SIMD instructions translated to scala
Re: [Qemu-devel] [Bug 1594069] Re: SIMD instructions translated to scalar host instructions
Mon, 20 Jun 2016 16:08:03 +0100
On 20 June 2016 at 15:05, Timothy Pearson <address@hidden> wrote:
> I mostly filed the bug report since I was seeing multiple different
> attempts to implement this, and even a proper patch series on the
> mailing list, but no movement at all toward integrating this feature
> into mainline qemu.
> What would be needed to e.g. make the patch series on the mailing list
> acceptable for merge?
The bare minimum is that things need to not break for any
guest x host combination. The RFC patchset from Kirill says
that it doesn't work for all ARM guest code, for instance.
It also needs to fall back cleanly if the backend doesn't support
vector ops, and I'm not sure if the RFC does that. It needs
to implement more than a single test "vector add". It needs
to be reasonably demonstrated that it's actually a win on
real-life code rather than a trivial microbenchmark. The
various concerns listed in the RFC cover letter need to be
discussed and addressed.
This is all certainly doable, but the missing thing is "nobody
is actually doing it", not "we didn't know about this".
An RFC patchset is a sketch of a design, and there's a long
way between that and committable code.
The ACM paper looks like a classic example of a bit of academic
work: maybe they did something interesting, but their intended
end output was a paper, not code, and they never submitted any
patches to us that I'm aware of. (And again, "academic prototype"
and "production code" are often far apart.)