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[Qemu-devel] [PATCH v2 05/14] Q35: implement property interfece to sever
From: |
Efimov Vasily |
Subject: |
[Qemu-devel] [PATCH v2 05/14] Q35: implement property interfece to several parameters |
Date: |
Wed, 22 Jun 2016 15:24:49 +0300 |
During creation of Q35 instance several parameters are set using direct access.
It violates Qemu device model. Correctly, the parameters should be handled as
object properties.
The patch adds four link type properties for fields:
mch.ram_memory
mch.pci_address_space
mch.system_memory
mch.address_space_io
And, it adds two size type properties for fields:
mch.below_4g_mem_size
mch.above_4g_mem_size
Signed-off-by: Efimov Vasily <address@hidden>
---
hw/pci-host/q35.c | 20 ++++++++++++++++++++
include/hw/i386/pc.h | 2 ++
include/hw/pci-host/q35.h | 5 +++++
3 files changed, 27 insertions(+)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 70f897e..03be05d 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -127,6 +127,10 @@ static Property mch_props[] = {
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
+ mch.below_4g_mem_size, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
+ mch.above_4g_mem_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -177,6 +181,22 @@ static void q35_host_initfn(Object *obj)
q35_host_get_mmcfg_size,
NULL, NULL, NULL, NULL);
+ object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.ram_memory,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.pci_address_space,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.system_memory,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.address_space_io,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
/* Leave enough space for the biggest MCFG BAR */
/* TODO: this matches current bios behaviour, but
* it's not a power of two, which means an MTRR
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index dc7503d..1e4e383 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -238,6 +238,8 @@ void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
+#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
+#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index c5c073d..8b4bde3 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -78,6 +78,11 @@ typedef struct Q35PCIHost {
* gmch part
*/
+#define MCH_HOST_PROP_RAM_MEM "ram-mem"
+#define MCH_HOST_PROP_PCI_MEM "pci-mem"
+#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
+#define MCH_HOST_PROP_IO_MEM "io-mem"
+
/* PCI configuration */
#define MCH_HOST_BRIDGE "MCH"
--
2.7.4
- [Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model., Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 01/14] ide: move headers to include folder, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 03/14] vmport: identify vmport type by macro TYPE_VMPORT, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 11/14] ICH9 LPC: move call of isa_bus_irqs to 'realize' method, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 02/14] pcspk: convert "pit" property type from ptr to link, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 07/14] pckbd: handle A20 IRQ as GPIO, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 04/14] pflash: make TYPE_CFI_PFLASH0{1, 2} macros public, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 14/14] ICH9 LPC: configure PCI IRQs routing internally, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 05/14] Q35: implement property interfece to several parameters,
Efimov Vasily <=
- [Qemu-devel] [PATCH v2 08/14] port92: handle A20 IRQ as GPIO, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 10/14] ICH9 LPC: handle GSI as qdev GPIO, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 12/14] isa: introduce wrapper isa_connect_gpio_out, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 06/14] pc_q35: configure Q35 instance using properties, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 13/14] MC146818 RTC: add GPIO access to output IRQ, Efimov Vasily, 2016/06/22
- [Qemu-devel] [PATCH v2 09/14] ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro public, Efimov Vasily, 2016/06/22
- Re: [Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model., Paolo Bonzini, 2016/06/22