[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v11 11/28] intel_iommu: handle interrupt remap enabl
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v11 11/28] intel_iommu: handle interrupt remap enable |
Date: |
Tue, 5 Jul 2016 16:19:12 +0800 |
Handle writting to IRE bit in global command register.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/intel_iommu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c793031..a12091e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1183,6 +1183,22 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool
en)
}
}
+/* Handle Interrupt Remap Enable/Disable */
+static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
+{
+ VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
+
+ if (en) {
+ s->intr_enabled = true;
+ /* Ok - report back to driver */
+ vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
+ } else {
+ s->intr_enabled = false;
+ /* Ok - report back to driver */
+ vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
+ }
+}
+
/* Handle write to Global Command Register */
static void vtd_handle_gcmd_write(IntelIOMMUState *s)
{
@@ -1207,6 +1223,10 @@ static void vtd_handle_gcmd_write(IntelIOMMUState *s)
/* Set/update the interrupt remapping root-table pointer */
vtd_handle_gcmd_sirtp(s);
}
+ if (changed & VTD_GCMD_IRE) {
+ /* Interrupt remap enable/disable */
+ vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
+ }
}
/* Handle write to Context Command Register */
--
2.4.11
[Qemu-devel] [PATCH v11 05/28] x86-iommu: introduce "intremap" property, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 06/28] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 07/28] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 08/28] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 09/28] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 10/28] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 11/28] intel_iommu: handle interrupt remap enable,
Peter Xu <=
[Qemu-devel] [PATCH v11 12/28] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 13/28] intel_iommu: add IR translation faults defines, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 14/28] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 15/28] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 16/28] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 17/28] intel_iommu: add support for split irqchip, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 18/28] x86-iommu: introduce IEC notifiers, Peter Xu, 2016/07/05
[Qemu-devel] [PATCH v11 19/28] ioapic: register IOMMU IEC notifier for ioapic, Peter Xu, 2016/07/05