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[Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector |
Date: |
Tue, 12 Jul 2016 12:14:51 +0100 |
When VP enters the Run state it starts execution from the reset vector.
Currently used CPU_INTERRUPT_WAKE does not do that if reset exception
base has been modified. Therefore fix that by simply resetting given VP.
Drop the usage of CPU_INTERRUPT_WAKE also in VP_STOP and instead raise
the CPU_INTERRUPT_HALT to halt a VP.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/misc/mips_cpc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd..6d34574 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
if (i & vp_run & ~cpc->vp_running) {
- cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
+ cpu_reset(cs);
cpc->vp_running |= i;
}
}
@@ -50,8 +50,7 @@ static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
if (i & vp_stop & cpc->vp_running) {
- cs->halted = 1;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+ cpu_interrupt(cs, CPU_INTERRUPT_HALT);
cpc->vp_running &= ~i;
}
}
--
2.7.4
- [Qemu-devel] [PULL 00/11] target-mips queue, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector,
Leon Alrae <=
- [Qemu-devel] [PULL 02/11] hw/mips: implement Global Interrupt Controller, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 07/11] target-mips: replace MIPS64R6-generic with the real I6400 CPU model, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 06/11] hw/mips_cmgcr: implement RESET_BASE register in CM GCR, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 11/11] target-mips: enable 10-bit ASIDs in I6400 CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 08/11] target-mips: add ASID mask field and replace magic values, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit, Leon Alrae, 2016/07/12
- Re: [Qemu-devel] [PULL 00/11] target-mips queue, Peter Maydell, 2016/07/12