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[Qemu-devel] [PULL v2 26/55] ioapic: register IOMMU IEC notifier for ioa
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 26/55] ioapic: register IOMMU IEC notifier for ioapic |
Date: |
Tue, 19 Jul 2016 20:52:55 +0300 |
From: Peter Xu <address@hidden>
Let IOAPIC the first consumer of x86 IOMMU IEC invalidation
notifiers. This is only used for split irqchip case, when vIOMMU
receives IR invalidation requests, IOAPIC will be notified to update
kernel irq routes. For simplicity, we just update all IOAPIC routes,
even if the invalidated entries are not IOAPIC ones.
Since now we are creating IOMMUs using "-device" parameter, IOMMU
device will be created after IOAPIC. We need to do the registration
after machine done by leveraging machine_done notifier.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
include/hw/i386/ioapic_internal.h | 2 ++
hw/intc/ioapic.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/include/hw/i386/ioapic_internal.h
b/include/hw/i386/ioapic_internal.h
index 5c901ae..d89ea1b 100644
--- a/include/hw/i386/ioapic_internal.h
+++ b/include/hw/i386/ioapic_internal.h
@@ -25,6 +25,7 @@
#include "hw/hw.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
+#include "qemu/notify.h"
#define MAX_IOAPICS 1
@@ -107,6 +108,7 @@ struct IOAPICCommonState {
uint8_t ioregsel;
uint32_t irr;
uint64_t ioredtbl[IOAPIC_NUM_PINS];
+ Notifier machine_done;
};
void ioapic_reset_common(DeviceState *dev);
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index c4469e4..819585d 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -31,6 +31,7 @@
#include "sysemu/kvm.h"
#include "target-i386/cpu.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/x86-iommu.h"
//#define DEBUG_IOAPIC
@@ -198,6 +199,16 @@ static void ioapic_update_kvm_routes(IOAPICCommonState *s)
#endif
}
+#ifdef CONFIG_KVM
+static void ioapic_iec_notifier(void *private, bool global,
+ uint32_t index, uint32_t mask)
+{
+ IOAPICCommonState *s = (IOAPICCommonState *)private;
+ /* For simplicity, we just update all the routes */
+ ioapic_update_kvm_routes(s);
+}
+#endif
+
void ioapic_eoi_broadcast(int vector)
{
IOAPICCommonState *s;
@@ -354,6 +365,24 @@ static const MemoryRegionOps ioapic_io_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void ioapic_machine_done_notify(Notifier *notifier, void *data)
+{
+#ifdef CONFIG_KVM
+ IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
+ machine_done);
+
+ if (kvm_irqchip_is_split()) {
+ X86IOMMUState *iommu = x86_iommu_get_default();
+ if (iommu) {
+ /* Register this IOAPIC with IOMMU IEC notifier, so that
+ * when there are IR invalidates, we can be notified to
+ * update kernel IR cache. */
+ x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
+ }
+ }
+#endif
+}
+
static void ioapic_realize(DeviceState *dev, Error **errp)
{
IOAPICCommonState *s = IOAPIC_COMMON(dev);
@@ -364,6 +393,8 @@ static void ioapic_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
ioapics[ioapic_no] = s;
+ s->machine_done.notify = ioapic_machine_done_notify;
+ qemu_add_machine_init_done_notifier(&s->machine_done);
}
static void ioapic_class_init(ObjectClass *klass, void *data)
--
MST
- [Qemu-devel] [PULL v2 16/55] acpi: add DMAR scope definition for root IOAPIC, (continued)
- [Qemu-devel] [PULL v2 16/55] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 17/55] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 18/55] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 19/55] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 20/55] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 21/55] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 22/55] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 23/55] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 24/55] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 25/55] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 26/55] ioapic: register IOMMU IEC notifier for ioapic,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 27/55] intel_iommu: Add support for Extended Interrupt Mode, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 28/55] intel_iommu: add SID validation for IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 29/55] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 30/55] kvm-irqchip: i386: add hook for add/remove virq, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 31/55] kvm-irqchip: x86: add msi route notify fn, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 32/55] kvm-irqchip: do explicit commit when update irq, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 33/55] intel_iommu: support all masks in interrupt entry cache invalidation, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 34/55] kvm-all: add trace events for kvm irqchip ops, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 35/55] intel_iommu: disallow kernel-irqchip=on with IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 36/55] virtio: Add typedef for handle_output, Michael S. Tsirkin, 2016/07/19