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[Qemu-devel] [PATCH v2 06/17] target-ppc: convert st[16, 32, 64]r to use
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro |
Date: |
Sat, 13 Aug 2016 00:04:32 +0530 |
Make byte-swap routines use the common GEN_QEMU_LOAD macro
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd16681..21092d0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2508,6 +2508,9 @@ GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
+GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
+GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
+
#define GEN_QEMU_STORE_64(stop, op) \
static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
TCGv_i64 val, \
@@ -2519,6 +2522,10 @@ static void glue(gen_qemu_, glue(stop,
_i64))(DisasContext *ctx, \
GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
+#if defined(TARGET_PPC64)
+GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
+#endif
+
#define GEN_LD(name, ldop, opc, type) \
static void glue(gen_, name)(DisasContext *ctx)
\
{ \
@@ -2842,34 +2849,15 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
#if defined(TARGET_PPC64)
/* ldbrx */
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
+/* stdbrx */
+GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
#endif /* TARGET_PPC64 */
/* sthbrx */
-static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
-
/* stwbrx */
-static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
-#if defined(TARGET_PPC64)
-/* stdbrx */
-static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
-}
-GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
-#endif /* TARGET_PPC64 */
-
/*** Integer load and store multiple ***/
/* lmw */
@@ -6614,7 +6602,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
#if defined(TARGET_PPC64)
GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
-GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
+GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
--
2.7.4
- [Qemu-devel] [PATCH v2 00/17] POWER9 TCG enablements - part4, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 03/17] target-ppc: convert ld[16, 32, 64]ur to use new macro, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 01/17] target-ppc: consolidate load operations, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 07/17] target-ppc: consolidate load with reservation, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 05/17] target-ppc: convert st64 to use new macro, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 02/17] target-ppc: convert ld64 to use new macro, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 04/17] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH v2 09/17] target-ppc: consolidate store conditional, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 10/17] target-ppc: add xxspltib instruction, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 08/17] target-ppc: move out stqcx impementation, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 11/17] target-ppc: implement darn instruction, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 13/17] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 12/17] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 14/17] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 15/17] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 17/17] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/08/12
- [Qemu-devel] [PATCH v2 16/17] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/08/12