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[Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruct
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction |
Date: |
Mon, 12 Sep 2016 12:11:40 +0530 |
From: Ravi Bangoria <address@hidden>
darn: Deliver A Random Number
Currently return invalid random number for all the case. This needs
proper algorithm to provide cryptographically suitable random data.
Reading from /dev/random can block and that is not an expected behaviour
while the cpu instruction is getting executed. Moreover, /dev/random
would only work for linux-user
Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 16 ++++++++++++++++
target-ppc/translate.c | 18 ++++++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e75d070..966f2ce 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -50,6 +50,8 @@ DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
+DEF_HELPER_0(darn32, tl)
+DEF_HELPER_0(darn64, tl)
#endif
DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 291fba0..51a9ac5 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -182,6 +182,22 @@ target_ulong helper_cnttzd(target_ulong t)
{
return ctz64(t);
}
+
+/* Return invalid random number.
+ *
+ * FIXME: Add rng backend or other mechanism to get cryptographically suitable
+ * random number
+ */
+target_ulong helper_darn32(void)
+{
+ return -1;
+}
+
+target_ulong helper_darn64(void)
+{
+ return -1;
+}
+
#endif
#if defined(TARGET_PPC64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 133c531..e9dad3f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -528,6 +528,8 @@ EXTRACT_HELPER(FPW, 16, 1);
/* addpcis */
EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+/* darn */
+EXTRACT_HELPER(L, 16, 2);
/*** Jump target decoding ***/
/* Immediate address */
@@ -1895,6 +1897,21 @@ static void gen_cnttzd(DisasContext *ctx)
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
}
+
+/* darn */
+static void gen_darn(DisasContext *ctx)
+{
+ int l = L(ctx->opcode);
+
+ if (l == 0) {
+ gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
+ } else if (l <= 2) {
+ /* Return 64-bit random for both CRN and RRN */
+ gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
+ } else {
+ tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
+ }
+}
#endif
/*** Integer rotate ***/
@@ -6212,6 +6229,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801,
PPC_NONE, PPC2_ISA205),
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE,
PPC2_PERM_ISA206),
#endif
--
2.7.4
- Re: [Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro, (continued)
- [Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 07/17] target-ppc: consolidate load with reservation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH RESEND v2 12/17] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 14/17] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 15/17] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/09/12