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[Qemu-devel] [PULL v5 11/18] tcg/s390: Add support for fence
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL v5 11/18] tcg/s390: Add support for fence |
Date: |
Wed, 14 Sep 2016 09:20:06 -0700 |
From: Pranith Kumar <address@hidden>
Cc: Alexander Graf <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.inc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 18aa16a..93ca944 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
#define FACILITY_EXT_IMM (1ULL << (63 - 21))
#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
+#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
static uint64_t facilities;
@@ -2169,6 +2170,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tgen_deposit(s, args[0], args[2], args[3], args[4]);
break;
+ case INDEX_op_mb:
+ /* The host memory model is quite strong, we simply need to
+ serialize the instruction stream. */
+ if (args[0] & TCG_MO_ST_LD) {
+ tcg_out_insn(s, RR, BCR,
+ facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2290,6 +2300,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
{ INDEX_op_deposit_i64, { "r", "0", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.7.4
- [Qemu-devel] [PULL v5 00/18] tcg queued patches, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 03/18] cpu-exec: Check -dfilter for -d cpu, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 01/18] tcg: Support arbitrary size + alignment, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 04/18] Introduce TCGOpcode for memory barrier, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 02/18] tcg: Merge GETPC and GETRA, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 05/18] tcg/i386: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 06/18] tcg/aarch64: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 07/18] tcg/arm: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 10/18] tcg/ppc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 11/18] tcg/s390: Add support for fence,
Richard Henderson <=
- [Qemu-devel] [PULL v5 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 15/18] target-arm: Generate fences in ARMv7 frontend, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 14/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 16/18] target-aarch64: Generate fences for aarch64, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 17/18] target-i386: Generate fences for x86, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 18/18] tcg: Optimize fence instructions, Richard Henderson, 2016/09/14
- Re: [Qemu-devel] [PULL v5 00/18] tcg queued patches, Peter Maydell, 2016/09/15