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[Qemu-devel] [V5 2/6] hw/i386: enforce SID verification
From: |
David Kiarie |
Subject: |
[Qemu-devel] [V5 2/6] hw/i386: enforce SID verification |
Date: |
Tue, 20 Sep 2016 20:40:42 +0300 |
Platform devices are now able to make interrupt request with
explicit SIDs hence remove unnecesary check for invalid SID.
Signed-off-by: David Kiarie <address@hidden>
---
hw/i386/intel_iommu.c | 72 ++++++++++++++++++++-------------------------
include/hw/i386/x86-iommu.h | 1 -
2 files changed, 32 insertions(+), 41 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 496d836..3f6da40 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2043,43 +2043,41 @@ static int vtd_irte_get(IntelIOMMUState *iommu,
uint16_t index,
return -VTD_FR_IR_IRTE_RSVD;
}
- if (sid != X86_IOMMU_SID_INVALID) {
- /* Validate IRTE SID */
- source_id = le32_to_cpu(entry->irte.source_id);
- switch (entry->irte.sid_vtype) {
- case VTD_SVT_NONE:
- VTD_DPRINTF(IR, "No SID validation for IRTE index %d", index);
- break;
-
- case VTD_SVT_ALL:
- mask = vtd_svt_mask[entry->irte.sid_q];
- if ((source_id & mask) != (sid & mask)) {
- VTD_DPRINTF(GENERAL, "SID validation for IRTE index "
- "%d failed (reqid 0x%04x sid 0x%04x)", index,
- sid, source_id);
- return -VTD_FR_IR_SID_ERR;
- }
- break;
+ /* Validate IRTE SID */
+ source_id = le32_to_cpu(entry->irte.source_id);
+ switch (entry->irte.sid_vtype) {
+ case VTD_SVT_NONE:
+ VTD_DPRINTF(IR, "No SID validation for IRTE index %d", index);
+ break;
- case VTD_SVT_BUS:
- bus_max = source_id >> 8;
- bus_min = source_id & 0xff;
- bus = sid >> 8;
- if (bus > bus_max || bus < bus_min) {
- VTD_DPRINTF(GENERAL, "SID validation for IRTE index %d "
- "failed (bus %d outside %d-%d)", index, bus,
- bus_min, bus_max);
- return -VTD_FR_IR_SID_ERR;
- }
- break;
+ case VTD_SVT_ALL:
+ mask = vtd_svt_mask[entry->irte.sid_q];
+ if ((source_id & mask) != (sid & mask)) {
+ VTD_DPRINTF(GENERAL, "SID validation for IRTE index "
+ "%d failed (reqid 0x%04x sid 0x%04x)", index,
+ sid, source_id);
+ return -VTD_FR_IR_SID_ERR;
+ }
+ break;
- default:
- VTD_DPRINTF(GENERAL, "Invalid SVT bits (0x%x) in IRTE index "
- "%d", entry->irte.sid_vtype, index);
- /* Take this as verification failure. */
+ case VTD_SVT_BUS:
+ bus_max = source_id >> 8;
+ bus_min = source_id & 0xff;
+ bus = sid >> 8;
+ if (bus > bus_max || bus < bus_min) {
+ VTD_DPRINTF(GENERAL, "SID validation for IRTE index %d "
+ "failed (bus %d outside %d-%d)", index, bus,
+ bus_min, bus_max);
return -VTD_FR_IR_SID_ERR;
- break;
}
+ break;
+
+ default:
+ VTD_DPRINTF(GENERAL, "Invalid SVT bits (0x%x) in IRTE index "
+ "%d", entry->irte.sid_vtype, index);
+ /* Take this as verification failure. */
+ return -VTD_FR_IR_SID_ERR;
+ break;
}
return 0;
@@ -2252,17 +2250,11 @@ static MemTxResult vtd_mem_ir_write(void *opaque,
hwaddr addr,
{
int ret = 0;
MSIMessage from = {}, to = {};
- uint16_t sid = X86_IOMMU_SID_INVALID;
from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
from.data = (uint32_t) value;
- if (!attrs.unspecified) {
- /* We have explicit Source ID */
- sid = attrs.requester_id;
- }
-
- ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
+ ret = vtd_interrupt_remap_msi(opaque, &from, &to, attrs.requester_id);
if (ret) {
/* TODO: report error */
VTD_DPRINTF(GENERAL, "int remap fail for addr 0x%"PRIx64
diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
index 5d05865..af869ab 100644
--- a/include/hw/i386/x86-iommu.h
+++ b/include/hw/i386/x86-iommu.h
@@ -32,7 +32,6 @@
OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
#define X86_IOMMU_PCI_DEVFN_MAX 256
-#define X86_IOMMU_SID_INVALID (0xffff)
typedef struct X86IOMMUState X86IOMMUState;
typedef struct X86IOMMUClass X86IOMMUClass;
--
2.1.4
- [Qemu-devel] [V5 0/6] AMD IOMMU interrupt remapping, David Kiarie, 2016/09/20
- [Qemu-devel] [V5 1/6] hw/msi: Allow platform devices to use explicit SID, David Kiarie, 2016/09/20
- [Qemu-devel] [V5 2/6] hw/i386: enforce SID verification,
David Kiarie <=
- [Qemu-devel] [V5 3/6] hw/iommu: Prepare for AMD IOMMU interrupt remapping, David Kiarie, 2016/09/20
- [Qemu-devel] [V5 4/6] hw/iommu: AMD IOMMU interrupt remapping, David Kiarie, 2016/09/20
- [Qemu-devel] [V5 5/6] hw/acpi: report IOAPIC on IVRS, David Kiarie, 2016/09/20
- [Qemu-devel] [V5 6/6] hw/iommu: share common code between IOMMUs, David Kiarie, 2016/09/20
- Re: [Qemu-devel] [V5 0/6] AMD IOMMU interrupt remapping, David Kiarie, 2016/09/30