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[Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation suppo
From: |
Sagar Karandikar |
Subject: |
[Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) |
Date: |
Mon, 26 Sep 2016 03:56:30 -0700 |
This patch set adds support for the RISC-V ISA [1] as a system-mode
target. It has been tested booting Linux and FreeBSD, passes the RISC-V
assembly test suite, and has had the riscv-torture [2] tester running on it for
a while now without any issues arising. This patch set supports RV64G and
RV32G.
Potentially useful references:
-RISC-V User Spec: See [3]. This spec is frozen.
-RISC-V Privileged Spec: See [4]. This spec is a draft, we implement v1.9.
-Spike, the reference simulator for the ISA: See [5].
The comments from an earlier RFC were addressed:
-We use QEMU's built-in softfloat
-cpu-qom.h merged into cpu.h
-remove active_tc/riscv-defs.h that were mirrored from MIPS
-Use DEF_HELPER_FLAGS_* where necessary
-DIV/REM now use movcond instead of branches
-handlers for arithmetic instructions and their "W" counterparts were merged to
reduce code duplication
-Updated to use tcg_gen_qemu_ld_tl(..., MO_SB) etc.
[1] https://riscv.org
[2] https://github.com/ucb-bar/riscv-torture
[3] https://content.riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf
[4]
https://content.riscv.org/wp-content/uploads/2016/07/riscv-privileged-v1.9-1.pdf
[5] https://github.com/riscv/riscv-isa-sim
Sagar Karandikar (18):
target-riscv: Add RISC-V target stubs and Maintainer
target-riscv: Add RISC-V Target stubs inside target-riscv/
target-riscv: Add initialization for translation
target-riscv: Add framework for instruction decode
target-riscv: Add Arithmetic instructions
target-riscv: Add JALR, Branch Instructions
target-riscv: Add Loads/Stores, FP Loads/Stores
target-riscv: Add Atomic Instructions
target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,
target-riscv: Add Single Precision Floating-Point Instructions
target-riscv: Add Double Precision Floating-Point Instructions
target-riscv: Add system instructions
target-riscv: Add CSR read/write helpers
target-riscv: softmmu/address translation support
target-riscv: Interrupt Handling
target-riscv: Timer Support
target-riscv: Add support for Host-Target Interface (HTIF) Devices
target-riscv: Add generic test board, activate target
MAINTAINERS | 7 +
arch_init.c | 2 +
configure | 6 +
cpus.c | 6 +
default-configs/riscv32-softmmu.mak | 38 +
default-configs/riscv64-softmmu.mak | 38 +
fpu/softfloat-specialize.h | 7 +-
hw/riscv/Makefile.objs | 5 +
hw/riscv/cpudevs.h | 17 +
hw/riscv/htif/elf_symb.c | 286 ++++++
hw/riscv/htif/elf_symb.h | 80 ++
hw/riscv/htif/htif.c | 423 +++++++++
hw/riscv/riscv_board.c | 264 ++++++
hw/riscv/riscv_int.c | 67 ++
hw/riscv/riscv_rtc.c | 230 +++++
include/elf.h | 2 +
include/hw/riscv/htif/htif.h | 61 ++
include/hw/riscv/riscv_rtc.h | 25 +
include/hw/riscv/riscv_rtc_internal.h | 3 +
include/sysemu/arch_init.h | 1 +
qapi-schema.json | 14 +-
target-riscv/Makefile.objs | 1 +
target-riscv/cpu.c | 154 +++
target-riscv/cpu.h | 497 ++++++++++
target-riscv/fpu_helper.c | 582 ++++++++++++
target-riscv/helper.c | 420 +++++++++
target-riscv/helper.h | 87 ++
target-riscv/instmap.h | 328 +++++++
target-riscv/op_helper.c | 577 ++++++++++++
target-riscv/translate.c | 1658 +++++++++++++++++++++++++++++++++
30 files changed, 5882 insertions(+), 4 deletions(-)
create mode 100644 default-configs/riscv32-softmmu.mak
create mode 100644 default-configs/riscv64-softmmu.mak
create mode 100644 hw/riscv/Makefile.objs
create mode 100644 hw/riscv/cpudevs.h
create mode 100644 hw/riscv/htif/elf_symb.c
create mode 100644 hw/riscv/htif/elf_symb.h
create mode 100644 hw/riscv/htif/htif.c
create mode 100644 hw/riscv/riscv_board.c
create mode 100644 hw/riscv/riscv_int.c
create mode 100644 hw/riscv/riscv_rtc.c
create mode 100644 include/hw/riscv/htif/htif.h
create mode 100644 include/hw/riscv/riscv_rtc.h
create mode 100644 include/hw/riscv/riscv_rtc_internal.h
create mode 100644 target-riscv/Makefile.objs
create mode 100644 target-riscv/cpu.c
create mode 100644 target-riscv/cpu.h
create mode 100644 target-riscv/fpu_helper.c
create mode 100644 target-riscv/helper.c
create mode 100644 target-riscv/helper.h
create mode 100644 target-riscv/instmap.h
create mode 100644 target-riscv/op_helper.c
create mode 100644 target-riscv/translate.c
--
2.9.3
- [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G),
Sagar Karandikar <=
- [Qemu-devel] [PATCH 06/18] target-riscv: Add JALR, Branch Instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 01/18] target-riscv: Add RISC-V target stubs and Maintainer, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 15/18] target-riscv: Interrupt Handling, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 07/18] target-riscv: Add Loads/Stores, FP Loads/Stores, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions, Sagar Karandikar, 2016/09/26