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Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions
From: |
Sagar Karandikar |
Subject: |
Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions |
Date: |
Tue, 27 Sep 2016 11:12:58 -0700 |
Hi Paolo,
There's a fork that has linux-user support. We'll get it added into the
downstream riscv-qemu repo and include that in the next patch set instead
of softmmu.
Thanks,
Sagar
On Mon, Sep 26, 2016 at 5:44 AM, Paolo Bonzini <address@hidden> wrote:
>
>
> On 26/09/2016 14:38, Bastian Koppelmann wrote:
> > On 09/26/2016 02:21 PM, Paolo Bonzini wrote:
> >>
> >>
> >> On 26/09/2016 12:56, Sagar Karandikar wrote:
> >>> +#ifndef CONFIG_USER_ONLY
> >>> +DEF_HELPER_4(csrrw, tl, env, tl, tl, tl)
> >>> +DEF_HELPER_5(csrrs, tl, env, tl, tl, tl, tl)
> >>> +DEF_HELPER_5(csrrc, tl, env, tl, tl, tl, tl)
> >>> +DEF_HELPER_2(sret, tl, env, tl)
> >>> +DEF_HELPER_2(mret, tl, env, tl)
> >>> +DEF_HELPER_1(tlb_flush, void, env)
> >>> +DEF_HELPER_1(fence_i, void, env)
> >>> +#endif /* !CONFIG_USER_ONLY */
> >>
> >> The system emulation spec is still in flux, I think we should only add
> >> user-mode emulation for now.
> >>
> >
> > Hi Paolo,
> >
> > by user-mode emulation you still mean softmmu and not linux-user, right?
> > So just drop the system instructions for now.
>
> I don't think that's possible; all RISC-V machines include at least
> M-mode, whose precise definitions requires the privileged interface
> specification which hasn't been finalized yet. So only linux-user is
> stable enough.
>
> In fact, based on some recent discussions on the RISC-V isa-dev mailing
> list, it looks like some memory protection features _beyond_ the
> privileged interface specification are in practice required to secure
> M-mode from the supervisor. I'm not sure what's the point in defining a
> separate mandatory M-mode (supervisor mode cannot even enable paging
> without help from M-mode, on the other hand a processor that only has M-
> and U-modes cannot enable paging) but not providing the tools to
> actually enforce privilege separation for it.
>
> All in all, while I'm happy that the RISC-V project uses QEMU for
> development, I don't think that the privileged interface specification
> is mature enough for inclusion in QEMU. It's very different for
> linux-user user-mode emulation of course, it's great to have that upstream.
>
> Thanks,
>
> Paolo
>
- [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions, (continued)
- [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 14/18] target-riscv: softmmu/address translation support, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 16/18] target-riscv: Timer Support, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions, Richard Henderson, 2016/09/26
[Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Richard Henderson, 2016/09/26
- Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Richard Henderson, 2016/09/27
[Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26