Re: [Qemu-devel] [PATCH 3/9] target-mips: Decode EVA load & store instructions

[James Hogan]

On Fri, Oct 07, 2016 at 05:05:30PM +0100, Yongbok Kim wrote:
> On 07/10/2016 16:48, James Hogan wrote:
> > On Fri, Oct 07, 2016 at 04:34:27PM +0100, Yongbok Kim wrote:
> >>> diff --git a/target-mips/translate.c b/target-mips/translate.c
> >>> index df2befbd5294..8506c39a359c 100644
> >>> --- a/target-mips/translate.c
> >>> +++ b/target-mips/translate.c
> >>> @@ -426,6 +426,24 @@ enum {
> >>>      OPC_EXTR_W_DSP     = 0x38 | OPC_SPECIAL3,
> >>>      OPC_DEXTR_W_DSP    = 0x3C | OPC_SPECIAL3,
> >>>  
> >>> +    /* EVA */
> >>> +    OPC_LWLE           = 0x19 | OPC_SPECIAL3,
> >>> +    OPC_LWRE           = 0x1A | OPC_SPECIAL3,
> >>> +    OPC_CACHEE         = 0x1B | OPC_SPECIAL3,
> >>> +    OPC_SBE            = 0x1C | OPC_SPECIAL3,
> >>> +    OPC_SHE            = 0x1D | OPC_SPECIAL3,
> >>> +    OPC_SCE            = 0x1E | OPC_SPECIAL3,
> >>> +    OPC_SWE            = 0x1F | OPC_SPECIAL3,
> >>> +    OPC_SWLE           = 0x21 | OPC_SPECIAL3,
> >>> +    OPC_SWRE           = 0x22 | OPC_SPECIAL3,
> >>> +    OPC_PREFE          = 0x23 | OPC_SPECIAL3,
> >>> +    OPC_LBUE           = 0x28 | OPC_SPECIAL3,
> >>> +    OPC_LHUE           = 0x29 | OPC_SPECIAL3,
> >>> +    OPC_LBE            = 0x2C | OPC_SPECIAL3,
> >>> +    OPC_LHE            = 0x2D | OPC_SPECIAL3,
> >>> +    OPC_LLE            = 0x2E | OPC_SPECIAL3,
> >>> +    OPC_LWE            = 0x2F | OPC_SPECIAL3,
> >>> +
> >>
> >> EVA for MIPS32 only. It is OK but it's worth mentioning it in the commit
> >> messages.
> > 
> > Are you referring to the lack of sde/lde instructions? My understanding
> > is that these were never defined since EVA is aimed at 32-bit code
> > (although segmentation control can still be implemented on a MIPS64
> > core, e.g. P6600).
> > 
> 
> Okay. What about microMIPS version of these instructions?

True. Should be easy enough to add (though whether Linux has ever been
tested with microMIPS + EVA is a whole other question... it should work
I'd think even without the unaligned access emulation of the microMIPS
versions implemented).

> >>> @@ -17981,13 +18042,57 @@ static void decode_opc_special3(CPUMIPSState 
> >>> *env, DisasContext *ctx)
> >>>  {
> >>>      int rs, rt, rd, sa;
> >>>      uint32_t op1, op2;
> >>> +    int16_t imm;
> >>>  
> >>>      rs = (ctx->opcode >> 21) & 0x1f;
> >>>      rt = (ctx->opcode >> 16) & 0x1f;
> >>>      rd = (ctx->opcode >> 11) & 0x1f;
> >>>      sa = (ctx->opcode >> 6) & 0x1f;
> >>> +    imm = (int16_t)ctx->opcode >> 7;
> >>
> >> imm = (int16_t) (ctx->opcode >> 7) & 0x1ff;
> > 
> > That won't sign extend it correctly.
> 
> That's true :) Use sextract32() then?

Okay

Cheers
James

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