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Re: [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc,
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 |
Date: |
Fri, 14 Oct 2016 18:35:51 +0100 |
On 14 October 2016 at 07:44, Alex Bennée <address@hidden> wrote:
>
> Peter Maydell <address@hidden> writes:
>
>> In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
>> branch, so the computed new value is written to r15 as a normal
>> value. The architecture says that in this case, bits [1:0] of
>> the value written must be ignored if we are in ARM mode (or
>> bit [0] ignored if in Thumb mode); this is a change from the
>> ARMv4/v5 specification that behaviour is UNPREDICTABLE.
>> Use the correct mask on the PC value when doing a non-interworking
>> store to PC.
>>
>> A popular library used on RaspberryPi uses this instruction
>> as part of a trick to determine whether it is running on
>> ARMv6 or ARMv7, and we were mishandling the sequence.
>>
>> Fixes bug: https://bugs.launchpad.net/bugs/1625295
>>
>> Reported-by: <address@hidden>
>> Signed-off-by: Peter Maydell <address@hidden>
>> Message-id: address@hidden
>
> I'm not sure how but this seems to have regressed my ARMv7 test images
> (currently Linux 4.7.7). With this change I see the guest spinning in
> the vectors table. If I comment out the change it boots.
>
> I'll dig some more but as this affects store_reg are there any cases
> when writing to the PC with offset bits would be correct?
Look for the patch I sent earlier that fixes a regression
in returning from exceptions to thumb addresses that are
only 2 aligned. That will probably fix it.
thanks
-- PMM
- [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list, (continued)
- [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace., Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 12/27] vmstateify tsc2005, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines, Peter Maydell, 2016/10/04
- [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables, Peter Maydell, 2016/10/04