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Re: [Qemu-devel] [PATCH v3 27/34] target-arm: emulate LL/SC using cmpxch
From: |
Pranith Kumar |
Subject: |
Re: [Qemu-devel] [PATCH v3 27/34] target-arm: emulate LL/SC using cmpxchg helpers |
Date: |
Thu, 20 Oct 2016 13:51:37 -0400 |
On Wed, Sep 14, 2016 at 12:38 PM, Richard Henderson <address@hidden> wrote:
> On 09/14/2016 09:03 AM, Alex Bennée wrote:
>>> > -/* Load/Store exclusive instructions are implemented by remembering
>>> > - the value/address loaded, and seeing if these are the same
>>> > - when the store is performed. This should be sufficient to implement
>>> > - the architecturally mandated semantics, and avoids having to monitor
>>> > - regular stores.
>>> > -
>>> > - In system emulation mode only one CPU will be running at once, so
>>> > - this sequence is effectively atomic. In user emulation mode we
>>> > - throw an exception and handle the atomic operation elsewhere. */
>> At least half of this comment is still relevant although it could be
>> tweaked to mention that we use an atomic cmpxchg for the store that will
>> fail if exlusive_val doesn't match the current state.
>>
>
> Added back
>
> /* Load/Store exclusive instructions are implemented by remembering
> the value/address loaded, and seeing if these are the same
> when the store is performed. This should be sufficient to implement
> the architecturally mandated semantics, and avoids having to monitor
> regular stores. The compare vs the remembered value is done during
> the cmpxchg operation, but we must compare the addresses manually. */
>
FYI, I do not see this in your v7 series.
--
Pranith
- Re: [Qemu-devel] [PATCH v3 27/34] target-arm: emulate LL/SC using cmpxchg helpers,
Pranith Kumar <=