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[Qemu-devel] [PATCH 5/9] hw/timer: QOM'ify m48txx_sysbus (pass 1)
From: |
xiaoqiang zhao |
Subject: |
[Qemu-devel] [PATCH 5/9] hw/timer: QOM'ify m48txx_sysbus (pass 1) |
Date: |
Sun, 23 Oct 2016 14:31:31 +0800 |
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao <address@hidden>
---
hw/timer/m48t59.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
index e46ca88..39e425e 100644
--- a/hw/timer/m48t59.c
+++ b/hw/timer/m48t59.c
@@ -765,30 +765,31 @@ static void m48t59_isa_realize(DeviceState *dev, Error
**errp)
}
}
-static int m48t59_init1(SysBusDevice *dev)
+static void m48t59_init1(Object *obj)
{
- M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
- M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
- Object *o = OBJECT(dev);
+ M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
+ M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
M48t59State *s = &d->state;
- Error *err = NULL;
s->model = u->info.model;
s->size = u->info.size;
sysbus_init_irq(dev, &s->IRQ);
- memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
+ memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
s->size);
- memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
- sysbus_init_mmio(dev, &s->iomem);
- sysbus_init_mmio(dev, &d->io);
- m48t59_realize_common(s, &err);
- if (err != NULL) {
- error_free(err);
- return -1;
- }
+ memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
+}
- return 0;
+static void m48t59_realize(DeviceState *dev, Error **errp)
+{
+ M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
+ M48t59State *s = &d->state;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_mmio(sbd, &d->io);
+ m48t59_realize_common(s, errp);
}
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
@@ -862,10 +863,9 @@ static Property m48t59_sysbus_properties[] = {
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
NvramClass *nc = NVRAM_CLASS(klass);
- k->init = m48t59_init1;
+ dc->realize = m48t59_realize;
dc->reset = m48t59_reset_sysbus;
dc->props = m48t59_sysbus_properties;
nc->read = m48txx_sysbus_read;
@@ -891,6 +891,7 @@ static const TypeInfo m48txx_sysbus_type_info = {
.name = TYPE_M48TXX_SYS_BUS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(M48txxSysBusState),
+ .instance_init = m48t59_init1,
.abstract = true,
.class_init = m48txx_sysbus_class_init,
.interfaces = (InterfaceInfo[]) {
--
2.9.3
- [Qemu-devel] [PATCH 0/9] QOM'ify work for sparc, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 7/9] hw/timer: QOM'ify slavio_timer, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 1/9] hw/misc: QOM'ify eccmemctl.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 3/9] hw/dma: QOM'ify sun4m_iommu.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 9/9] hw/sparc64: QOM'ify sun4u.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 4/9] hw/misc: QOM'ify slavio_misc.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 5/9] hw/timer: QOM'ify m48txx_sysbus (pass 1),
xiaoqiang zhao <=
- [Qemu-devel] [PATCH 8/9] hw/sparc: QOM'ify sun4m.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 2/9] hw/dma: QOM'ify sparc32_dma.c, xiaoqiang zhao, 2016/10/23
- [Qemu-devel] [PATCH 6/9] hw/timer: QOM'ify m48txx_sysbus (pass 2), xiaoqiang zhao, 2016/10/23