Re: [Qemu-devel] [PATCH 3/3] target-m68k: shift ops manage word and byte operands

[Richard Henderson]

On 10/27/2016 12:09 PM, Laurent Vivier wrote:
> @@ -562,7 +562,7 @@ static void gen_flush_flags(DisasContext *s)
>      s->cc_op_synced = 1;
>  }
>
> -static TCGv gen_extend(TCGv val, int opsize, int sign)
> +static inline TCGv gen_extend(TCGv val, int opsize, int sign)
>  {
>      TCGv tmp;

Fold this hunk back into patch 2, to eliminate both extraneous changes. 
Alternately, drop this hunk to let the compiler decide on inlining.

> +                /* mask of sign bit */
> +                tcg_gen_sari_i32(t0, reg, 31);
> +                tcg_gen_shri_i32(t0, t0, bits - count);
> +                tcg_gen_shri_i32(t1, reg, bits - count);
> +                tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1);

If you use sari for that third shift, doesn't that make the second shift 
unnecessary?

> +        tcg_gen_mov_i32(QREG_CC_V, zero);

Better to just use movi with 0.


r~