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[Qemu-devel] [PULL for-2.8 04/15] target-sparc: Use MMU_PHYS_IDX for byp
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL for-2.8 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis |
Date: |
Mon, 31 Oct 2016 09:52:42 -0600 |
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ee7bbc4..86432ac 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2046,6 +2046,11 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
mem_idx = MMU_KERNEL_IDX;
type = GET_ASI_DIRECT;
break;
+ case ASI_M_BYPASS: /* MMU passthrough */
+ case ASI_LEON_BYPASS: /* LEON MMU passthrough */
+ mem_idx = MMU_PHYS_IDX;
+ type = GET_ASI_DIRECT;
+ break;
}
} else {
gen_exception(dc, TT_PRIV_INSN);
@@ -2066,6 +2071,14 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
type = GET_ASI_EXCP;
} else {
switch (asi) {
+ case ASI_REAL: /* Bypass */
+ case ASI_REAL_IO: /* Bypass, non-cacheable */
+ case ASI_REAL_L: /* Bypass LE */
+ case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
+ case ASI_TWINX_REAL: /* Real address, twinx */
+ case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
+ mem_idx = MMU_PHYS_IDX;
+ break;
case ASI_N: /* Nucleus */
case ASI_NL: /* Nucleus LE */
case ASI_TWINX_N:
@@ -2123,6 +2136,10 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
break;
}
switch (asi) {
+ case ASI_REAL:
+ case ASI_REAL_IO:
+ case ASI_REAL_L:
+ case ASI_REAL_IO_L:
case ASI_N:
case ASI_NL:
case ASI_AIUP:
@@ -2135,6 +2152,8 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
case ASI_PL:
type = GET_ASI_DIRECT;
break;
+ case ASI_TWINX_REAL:
+ case ASI_TWINX_REAL_L:
case ASI_TWINX_N:
case ASI_TWINX_NL:
case ASI_TWINX_AIUP:
--
2.7.4
- [Qemu-devel] [PULL for-2.8 00/15] target-sparc updates, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 01/15] target-sparc: Use overalignment flags for twinx and block asis, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis,
Richard Henderson <=
- [Qemu-devel] [PULL for-2.8 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 11/15] target-sparc: Implement ldqf and stqf inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 13/15] target-sparc: Remove MMU_MODE*_SUFFIX, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 10/15] target-sparc: Remove asi helper code handled inline, Richard Henderson, 2016/10/31
- [Qemu-devel] [PULL for-2.8 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl, Richard Henderson, 2016/10/31