[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions

From: Laurent Vivier
Subject: [Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions
Date: Tue, 1 Nov 2016 21:03:28 +0100

This series is another subset of the series I sent in May:

It must be applied on top of series:
"target-m68k: 680x0 instruction set, part 2"

This subset contains reworked patches of mul and div instructions:
- "add 64bit mull": correctly set QREG_CC_V,
- "inline divu/divs": don't inline divu/divs, but update
   existing functions to manage 680x0 div instructions

I've checked it doesn't break coldfire support:
but it can't boot a 680x0 processor kernel.

- divull/divsll: build correctly the 64bit num value
                 check overflow as it is done in divsw

- mull: manage the case where Dl == Dh
- divu/divs: move all the mechanic to helpers,
  and pass the register number to directly set
  the result
- Free "rem" and "quot" in "divl".

Laurent Vivier (2):
  target-m68k: add 64bit mull
  target-m68k: add 680x0 divu/divs variants

 linux-user/main.c       |   7 ++
 target-m68k/cpu.h       |   4 --
 target-m68k/helper.h    |   8 ++-
 target-m68k/op_helper.c | 182 +++++++++++++++++++++++++++++++++++++++++-------
 target-m68k/qregs.def   |   2 -
 target-m68k/translate.c | 146 +++++++++++++++++++++++++-------------
 6 files changed, 267 insertions(+), 82 deletions(-)


reply via email to

[Prev in Thread] Current Thread [Next in Thread]