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[Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines |
Date: |
Fri, 4 Nov 2016 21:50:05 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target-sparc/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 687e158..b41f5c5 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -304,19 +304,36 @@ enum {
#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
+#define TTE_NFO_BIT_UA2005 (1ULL << 62)
+#define TTE_USED_BIT_UA2005 (1ULL << 47)
+#define TTE_LOCKED_BIT_UA2005 (1ULL << 61)
+#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11)
+#define TTE_PRIV_BIT_UA2005 (1ULL << 8)
+#define TTE_W_OK_BIT_UA2005 (1ULL << 6)
+
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
+#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
+
+#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005)
+#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005)
+#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005)
+#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
+#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005)
+#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005)
+
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
+#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
--
1.8.3.1
- [Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2016/11/04