[Qemu-devel] [PATCH v4 0/2] target-m68k: add movem, BCD and CAS instructions

[Laurent Vivier]

This series is another subset of the series I sent in May:
https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg00501.html

This subset contains reworked patches for:
- abcd/nbcd/sbcd: remove inline, delay write back to memory and
  use only 3 digits (and extract it from the bifield patch as
  it was squashed into it)
- movem: delay the update of the registers to the end of the load
  sequence to be able to restart the operation in case of page
  fault, and manage the 68020+ <-> 68000/68010 special case
- cas/cas2: rewrite according Richard's comments,
  and use cmpxchg() in cas.

I've checked it doesn't break coldfire support:
http://wiki.qemu.org/download/coldfire-test-0.1.tar.bz2
but it can't boot a 680x0 processor kernel.

v4:
- bcd: simplify bcd_flags
- cas: use cpu_ldX_data_ra()/cpu_stX_data_ra()
           helper_atomic_cmpxchgq_be()
       fix address of second cmpxchgq() (use a2 instead of a1)
       manage invalid size in opcode_table

v3:
- This series must be applied on top of m68k-for-2.9 branch
- remove movem as it has been applied from another series
- bcd: use less bits, use 8bit immediate
- cas2: use CC_OP_CMPW  in cas2w,
        check CONFIG_ATOMIC64,
        call HELPER(cas2l) from INSN(cas2l)
v2:
- movem: don't use temp variable mask2
- bcd: delay register write back
       fix bcd_add() to add X
       define bcd_sub() instead of bsd_neg()
- cas2: make it atomic with "parallel_cpus" and
        cpu_loop_exit_atomic() (and 64bit cmpxchg()
        if possible)

Thanks,
Laurent

Laurent Vivier (2):
  target-m68k: add abcd/sbcd/nbcd
  target-m68k: add cas/cas2 ops

 target-m68k/helper.h    |   2 +
 target-m68k/op_helper.c | 109 ++++++++++++++
 target-m68k/translate.c | 369 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 480 insertions(+)

-- 
2.7.4