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Re: [Qemu-devel] [PATCH v6 00/19] Remaining MTTCG Base patches and ARM e

From: Paolo Bonzini
Subject: Re: [Qemu-devel] [PATCH v6 00/19] Remaining MTTCG Base patches and ARM enablement
Date: Wed, 9 Nov 2016 16:11:26 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0

On 09/11/2016 15:57, Alex Bennée wrote:
> The one outstanding question is how to deal with the TLB flush
> semantics of the various guest architectures. Currently flushes to
> other vCPUs will happen at the end of their currently executing
> Translation Block which could mean the originating vCPU makes
> assumptions about flushes having been completed when they haven't. In
> practice this hasn't been a problem and I haven't been able to
> construct a test case so far that would fail in such a case. This is
> probably because most tear downs of the other vCPU TLBs tend to be
> done while the other vCPUs are not doing much. If anyone can come up
> with a test case that would fail if this assumption isn't met then
> please let me know.

Have you tried implementing ARM's DMB semantics correctly?


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