[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 01/19] bitops: fix rol/ror when shift is zero
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 01/19] bitops: fix rol/ror when shift is zero |
Date: |
Tue, 15 Nov 2016 13:48:46 +1100 |
From: Nikunj A Dadhania <address@hidden>
All the variants for rol/ror have a bug in case where the shift == 0.
For example rol32, would generate:
return (word << 0) | (word >> 32);
Which though works, would be flagged as a runtime error on clang's
sanitizer.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 98fb005..1881284 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long hweight_long(unsigned long w)
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> (8 - shift));
+ return (word << shift) | (word >> ((8 - shift) & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << (8 - shift));
+ return (word >> shift) | (word << ((8 - shift) & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> (16 - shift));
+ return (word << shift) | (word >> ((16 - shift) & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int
shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << (16 - shift));
+ return (word >> shift) | (word << ((16 - shift) & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int
shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> (32 - shift));
+ return (word << shift) | (word >> ((32 - shift) & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int
shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << (32 - shift));
+ return (word >> shift) | (word << ((32 - shift) & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int
shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> (64 - shift));
+ return (word << shift) | (word >> ((64 - shift) & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int
shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << (64 - shift));
+ return (word >> shift) | (word << ((64 - shift) & 63));
}
/**
--
2.7.4
- [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 01/19] bitops: fix rol/ror when shift is zero,
David Gibson <=
- [Qemu-devel] [PULL 03/19] target-ppc: add vrldnm and vrlwnm instructions, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 02/19] target-ppc: add vrldnmi and vrlwmi instructions, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 16/19] ppc/pnv: fix xscom address translation for POWER9, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 06/19] ppc/pnv: fix compile breakage on old gcc, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 08/19] target-ppc: Implement bcdcfn. instruction, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 13/19] FU exceptions should carry a cause (IC), David Gibson, 2016/11/14
- [Qemu-devel] [PULL 04/19] target-ppc: add vprtyb[w/d/q] instructions, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 07/19] ppc: Remove some stub POWER6 models, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 14/19] spapr-vty: Fix bad assert() statement, David Gibson, 2016/11/14
- [Qemu-devel] [PULL 09/19] target-ppc: Implement bcdctn. instruction, David Gibson, 2016/11/14