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Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts |
Date: |
Mon, 28 Nov 2016 06:54:12 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 |
On 11/27/2016 11:35 AM, Laurent Vivier wrote:
>> > + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
> This does not extract correctly the C flag when the opsize is word or byte.
> I think we should use a shift instead:
>
> - tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
> -
> - /* Note that C=0 if shift count is 0, and we get that for free. */
> + if (opsize == OS_LONG) {
> + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
> + /* Note that C=0 if shift count is 0, and we get that for
> free. */
> + } else {
> + TCGv zero = tcg_const_i32(0);
> + tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
> + tcg_gen_shri_i64(t64, t64, bits);
> + tcg_gen_extrl_i64_i32(QREG_CC_C, t64);
> + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
> + s32, zero, zero, QREG_CC_C);
> + tcg_temp_free(zero);
> + }
>
> Do you have a better idea?
if (opsize == OS_LONG) {
tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
} else {
tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
}
Since we zero-extend the input from bits, it's still true that a zero shift
gets C=0 for free.
r~
[Qemu-devel] [PATCH v2 4/5] target-m68k: Implement bitfield ops for registers, Richard Henderson, 2016/11/09
[Qemu-devel] [PATCH v2 5/5] target-m68k: Implement bitfield ops for memory, Richard Henderson, 2016/11/09
Re: [Qemu-devel] [PATCH v2 0/5] target-m68k-patches, Laurent Vivier, 2016/11/09