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[Qemu-devel] [PATCH 44/65] tcg/s390: Handle clz opcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 44/65] tcg/s390: Handle clz opcode |
Date: |
Fri, 23 Dec 2016 20:00:21 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.h | 2 +-
tcg/s390/tcg-target.inc.c | 36 +++++++++++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 3ac2dc9..22500ba 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -110,7 +110,7 @@ extern uint64_t s390_facilities;
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_clz_i64 0
+#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM)
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5275297..e8d56a0 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -50,7 +50,7 @@
#define TCG_REG_NONE 0
/* A scratch register that may be be used throughout the backend. */
-#define TCG_TMP0 TCG_REG_R14
+#define TCG_TMP0 TCG_REG_R1
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG TCG_REG_R13
@@ -133,6 +133,7 @@ typedef enum S390Opcode {
RRE_DLR = 0xb997,
RRE_DSGFR = 0xb91d,
RRE_DSGR = 0xb90d,
+ RRE_FLOGR = 0xb983,
RRE_LGBR = 0xb906,
RRE_LCGR = 0xb903,
RRE_LGFR = 0xb914,
@@ -1241,6 +1242,33 @@ static void tgen_movcond(TCGContext *s, TCGType type,
TCGCond c, TCGReg dest,
}
}
+static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
+ TCGArg a2, int a2const)
+{
+ /* Since this sets both R and R+1, we have no choice but to store the
+ result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
+ QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
+ tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
+
+ if (a2const && a2 == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
+ } else {
+ if (a2const) {
+ tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
+ }
+ if (s390_facilities & FACILITY_LOAD_ON_COND) {
+ /* Emit: if (one bit found) dest = r0. */
+ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
+ } else {
+ /* Emit: if (no one bit found) goto over; dest = r0; over: */
+ tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
+ tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
+ }
+ }
+}
+
static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
int ofs, int len, int z)
{
@@ -2181,6 +2209,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tgen_extract(s, args[0], args[1], args[2], args[3]);
break;
+ case INDEX_op_clz_i64:
+ tgen_clz(s, args[0], args[1], args[2], const_args[2]);
+ break;
+
case INDEX_op_mb:
/* The host memory model is quite strong, we simply need to
serialize the instruction stream. */
@@ -2304,6 +2336,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_bswap32_i64, { "r", "r" } },
{ INDEX_op_bswap64_i64, { "r", "r" } },
+ { INDEX_op_clz_i64, { "r", "r", "ri" } },
+
{ INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } },
{ INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } },
--
2.9.3
- [Qemu-devel] [PATCH 32/65] target-ppc: Use clz and ctz opcodes, (continued)
- [Qemu-devel] [PATCH 32/65] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 31/65] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 33/65] target-s390x: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 35/65] target-tricore: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 38/65] target-arm: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 39/65] target-i386: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 41/65] tcg/aarch64: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 43/65] tcg/mips: Handle clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 37/65] target-xtensa: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 44/65] tcg/s390: Handle clz opcode,
Richard Henderson <=
- [Qemu-devel] [PATCH 40/65] tcg/ppc: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 42/65] tcg/arm: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 52/65] target-tricore: Use clrsb helper, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 45/65] tcg/i386: Fuly convert tcg_target_op_def, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 47/65] tcg/i386: Allow bmi2 shiftx to have non-matching operands, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 53/65] target-xtensa: Use clrsb helper, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 50/65] tcg: Add helpers for clrsb, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 56/65] target-ppc: Use ctpop helper, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 59/65] target-tilegx: Use ctpop helper, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 46/65] tcg/i386: Hoist common arguments in tcg_out_op, Richard Henderson, 2016/12/23