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Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

From: mar.krzeminski
Subject: Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.
Date: Mon, 9 Jan 2017 20:04:55 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1

W dniu 09.01.2017 o 11:46, Peter Maydell pisze:
On 4 January 2017 at 22:06, Jean-Christophe Dubois <address@hidden> wrote:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.

This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
a SPI flash memory.

Whith this path the CS signal is correctly asserted and deasserted arround
memory access.

Assertion level is now based on SPI device configuration.

This was tested by:
* booting linux on Sabrelite Qemu emulator.
* booting xvisor on Sabrelite Qemu emultor.

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Acked-by: Marcin KrzemiƄski <address@hidden>
  static void imx_spi_reset(DeviceState *dev)
      IMXSPIState *s = IMX_SPI(dev);
+    uint32_t i;


@@ -243,6 +263,11 @@ static void imx_spi_reset(DeviceState *dev)

      s->burst_length = 0;
+    /* Disable all CS lines */
+    for (i = 0; i < 4; i++) {
+        qemu_set_irq(s->cs_lines[i], !imx_spi_channel_pol(s, i));
+    }
Calling qemu_set_irq() in a device reset function is a bit
tricky, because in a full system reset the device at the other
end might have already reset or might not, and calling into
its handler function for the irq line change might provoke
an unwanted change of its state. We don't really have a coherent
model here but for the moment we just try to avoid calling
set_irq in a reset method.
JC, if you remove qemu_set_irq() call from reset, at least m25p80 behavior
should not change since m25p80 reset handler will reset it's whole internal state.


-- PMM

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