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[Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyp
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode |
Date: |
Wed, 11 Jan 2017 21:19:47 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/ldst_helper.c | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 387732d..301616b 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -293,6 +293,20 @@ static inline target_ulong asi_address_mask(CPUSPARCState
*env,
}
return addr;
}
+
+static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
+{
+ /* ASIs >= 0x80 are user mode.
+ * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
+ * ASIs <= 0x2f are super mode.
+ */
+ if (asi < 0x80
+ && !cpu_hypervisor_mode(env)
+ && (!cpu_supervisor_mode(env)
+ || (asi >= 0x30 && cpu_has_hypervisor(env)))) {
+ cpu_raise_exception_ra(env, TT_PRIV_ACT, ra);
+ }
+}
#endif
static void do_check_align(CPUSPARCState *env, target_ulong addr,
@@ -1118,13 +1132,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr,
asi &= 0xff;
- if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
- || (cpu_has_hypervisor(env)
- && asi >= 0x30 && asi < 0x80
- && !(env->hpstate & HS_PRIV))) {
- cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
- }
-
+ do_check_asi(env, asi, GETPC());
do_check_align(env, addr, size - 1, GETPC());
addr = asi_address_mask(env, asi, addr);
@@ -1423,13 +1431,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
addr, target_ulong val,
asi &= 0xff;
- if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
- || (cpu_has_hypervisor(env)
- && asi >= 0x30 && asi < 0x80
- && !(env->hpstate & HS_PRIV))) {
- cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
- }
-
+ do_check_asi(env, asi, GETPC());
do_check_align(env, addr, size - 1, GETPC());
addr = asi_address_mask(env, asi, addr);
--
1.8.3.1
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines, (continued)
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v2 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 28/30] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2017/01/11