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[Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines |
Date: |
Wed, 11 Jan 2017 18:55:40 -0800 |
From: Artyom Tarasenko <address@hidden>
Signed-off-by: Artyom Tarasenko <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/sparc/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 687e158..b41f5c5 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -304,19 +304,36 @@ enum {
#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
+#define TTE_NFO_BIT_UA2005 (1ULL << 62)
+#define TTE_USED_BIT_UA2005 (1ULL << 47)
+#define TTE_LOCKED_BIT_UA2005 (1ULL << 61)
+#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11)
+#define TTE_PRIV_BIT_UA2005 (1ULL << 8)
+#define TTE_W_OK_BIT_UA2005 (1ULL << 6)
+
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
+#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
+
+#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005)
+#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005)
+#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005)
+#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
+#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005)
+#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005)
+
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
+#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
--
2.9.3
- [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines,
Richard Henderson <=
- [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps, Richard Henderson, 2017/01/11