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[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs |
Date: |
Wed, 11 Jan 2017 18:56:03 -0800 |
From: Artyom Tarasenko <address@hidden>
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.
"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"
Integer stores of all sizes are allowed with these ASIs.
Signed-off-by: Artyom Tarasenko <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/sparc/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 53c327d..e929169 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2321,8 +2321,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv
addr,
case GET_ASI_EXCP:
break;
case GET_ASI_DTWINX: /* Reserved for stda. */
+#ifndef TARGET_SPARC64
gen_exception(dc, TT_ILL_INSN);
break;
+#else
+ if (!(dc->def->features & CPU_FEATURE_HYPV)) {
+ /* Pre OpenSPARC CPUs don't have these */
+ gen_exception(dc, TT_ILL_INSN);
+ return;
+ }
+ /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
+ * are ST_BLKINIT_ ASIs */
+ /* fall through */
+#endif
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
--
2.9.3
- [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, (continued)
- [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs,
Richard Henderson <=
- [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c, Richard Henderson, 2017/01/11
- [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Richard Henderson, 2017/01/11
- Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support, no-reply, 2017/01/11
- Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Peter Maydell, 2017/01/13
- [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Artyom Tarasenko, 2017/01/18