Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

[Stafford Horne]

On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote:
> On 01/26/2017 05:12 AM, Stafford Horne wrote:
> > I just sent you a mail with a link to my kernel for download.
> > 
> > One thing I noticed is you passed '-append console=ttyS0' I think that
> > does nothing on openrisc since as far as I know openrisc only gets boot
> > params from the device tree file. I tried with and without it and got no
> > differences.
> 
> That was just reflex, wondering where the output went.
> 
> > Another thing, I am using a 'late' version of gcc built with musl cross [1]
> > , I dont think it would make a difference, but maybe?
> 
> I think that's likely the difference.  I can indeed boot your kernel.

OK, you can try to build with the musl-cross link I sent you.

  https://github.com/openrisc/musl-cross/tree/or1k

Also, for the linux kernel crosstool project I am working on getting
their toolchain updated to support l.swa/l.lwa.   I have posted some
binaries here (but no libc needed for the kernel):

  http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/

The official ones are all here (below), but much too old to support openrisc
modern instructions.

  https://www.kernel.org/pub/tools/crosstool/

-Stafford