[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage
From: |
P J P |
Subject: |
[Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage |
Date: |
Tue, 31 Jan 2017 17:54:14 +0530 |
From: Prasad J Pandit <address@hidden>
Hello,
In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode
register is used to control 's->blkcnt' value. One, this bit is not
relevant in single block transfers. Second, Transfer Mode register
value could be set such that 's->blkcnt' would not see an update
during multi block transfers. Thus leading to an infinite loop.
This patch set attempts to correct 'Block Count Enable' bit usage.
Thank you.
--
Prasad J Pandit (2):
sd: sdhci: check transfer mode register in multi block transfer
sd: sdhci: block count enable not relevant in single block transfer
hw/sd/sdhci.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
--
2.9.3
- [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage,
P J P <=