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[Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest
From: |
Kirill Batuzov |
Subject: |
[Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest registers as globals |
Date: |
Wed, 1 Feb 2017 15:18:11 +0300 |
To support vector guest registers as globals we need to do two things:
1) create corresponding globals,
2) mark which globals can overlap,
Signed-off-by: Kirill Batuzov <address@hidden>
---
target/arm/translate.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 493c627..d7578e2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -65,6 +65,8 @@ static TCGv_i32 cpu_R[16];
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr;
TCGv_i64 cpu_exclusive_val;
+static TCGv_v128 cpu_Q[16];
+static TCGv_v64 cpu_D[32];
/* FIXME: These should be removed. */
static TCGv_i32 cpu_F0s, cpu_F1s;
@@ -72,10 +74,20 @@ static TCGv_i64 cpu_F0d, cpu_F1d;
#include "exec/gen-icount.h"
-static const char *regnames[] =
+static const char *regnames_r[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
+static const char *regnames_q[] =
+ { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+ "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" };
+
+static const char *regnames_d[] =
+ { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+ "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
+ "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" };
+
/* initialize TCG globals. */
void arm_translate_init(void)
{
@@ -87,8 +99,22 @@ void arm_translate_init(void)
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUARMState, regs[i]),
- regnames[i]);
+ regnames_r[i]);
+ }
+ for (i = 0; i < 16; i++) {
+ cpu_Q[i] = tcg_global_mem_new_v128(cpu_env,
+ offsetof(CPUARMState,
+ vfp.regs[2 * i]),
+ regnames_q[i]);
}
+ for (i = 0; i < 32; i++) {
+ cpu_D[i] = tcg_global_mem_new_v64(cpu_env,
+ offsetof(CPUARMState, vfp.regs[i]),
+ regnames_d[i]);
+ }
+
+ tcg_detect_overlapping_temps(&tcg_ctx);
+
cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF");
cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");
cpu_VF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), "VF");
--
2.1.4
- [Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 15/20] tcg: introduce new TCGMemOp - MO_128, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 07/20] tcg: allow globals to overlap, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 20/20] tcg/README: update README to include information about vector opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 08/20] tcg: add vector addition operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 17/20] softmmu: create helpers for vector loads, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 06/20] tcg: use results of alias analysis in liveness analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 10/20] target/arm: use vector opcode to handle vadd.<size> instruction, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 11/20] tcg/i386: add support for vector opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 03/20] tcg: support representing vector type with smaller vector or scalar types, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest registers as globals,
Kirill Batuzov <=
- [Qemu-devel] [PATCH v2 01/20] tcg: add support for 128bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 04/20] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 02/20] tcg: add support for 64bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 05/20] tcg: add simple alias analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 16/20] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 13/20] tcg/i386: support remaining vector addition operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 18/20] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 14/20] tcg: do not rely on exact values of MO_BSWAP or MO_SIGN in backend, Kirill Batuzov, 2017/02/01