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[Qemu-devel] [PULL 081/107] target-ppc: Add xvxsigsp instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 081/107] target-ppc: Add xvxsigsp instruction |
Date: |
Thu, 2 Feb 2017 16:14:19 +1100 |
From: Nikunj A Dadhania <address@hidden>
xvxsigsp: VSX Vector Extract Significand Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 20 ++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 24 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 77f68e9..4da83d9 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3026,3 +3026,23 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_XXPERM(xxperm, 0)
VSX_XXPERM(xxpermr, 1)
+
+void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xb;
+ uint32_t exp, i, fraction;
+
+ getVSR(xB(opcode), &xb, env);
+ memset(&xt, 0, sizeof(xt));
+
+ for (i = 0; i < 4; i++) {
+ exp = (xb.VsrW(i) >> 23) & 0xFF;
+ fraction = xb.VsrW(i) & 0x7FFFFF;
+ if (exp != 0 && exp != 255) {
+ xt.VsrW(i) = fraction | 0x00800000;
+ } else {
+ xt.VsrW(i) = fraction;
+ }
+ }
+ putVSR(xT(opcode), &xt, env);
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3cac050..ae14da4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -545,6 +545,7 @@ DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
+DEF_HELPER_2(xvxsigsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 7b26f75..4e57af7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1430,6 +1430,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
tcg_gen_andi_i64(xtl, xtl, 0x7FF);
}
+GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index a3061ce..2c4f641 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -128,6 +128,7 @@ GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
- [Qemu-devel] [PULL 100/107] target-ppc: Add xvtstdc[sp, dp] instructions, (continued)
- [Qemu-devel] [PULL 100/107] target-ppc: Add xvtstdc[sp, dp] instructions, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 077/107] target-ppc: Add xviexpsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 058/107] target-ppc: Add xsxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 072/107] ppc: Implement bcds. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-devel] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 097/107] target/ppc/cpu-models: Fix/remove bad CPU aliases, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 081/107] target-ppc: Add xvxsigsp instruction,
David Gibson <=
- [Qemu-devel] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 080/107] target-ppc: Add xvxexpdp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-devel] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu class definition, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 085/107] ppc: Implement bcdtrunc. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 086/107] ppc: Implement bcdutrunc. instruction, David Gibson, 2017/02/02
- [Qemu-devel] [PULL 089/107] target-ppc: Add xsdivqp instruction, David Gibson, 2017/02/02