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[Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling statu
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling status registers |
Date: |
Wed, 8 Feb 2017 20:51:36 -0800 |
From: Stafford Horne <address@hidden>
I am working on testing instruction emulation patches for the linux
kernel. During testing I found these 2 issues:
- sets DSX (delay slot exception) but never clears it
- EEAR for illegal insns should point to the bad exception (as per
openrisc spec) but its not
This patch fixes these two issues by clearing the DSX flag when not in a
delay slot and by setting EEAR to exception PC when handling illegal
instruction exceptions.
After this patch the openrisc kernel with latest patches boots great on
qemu and instruction emulation works.
Cc: address@hidden
Cc: address@hidden
Signed-off-by: Stafford Horne <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/interrupt.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e43fc84..a243eb2 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
env->epcr -= 4;
+ } else {
+ env->sr &= ~SR_DSX;
}
if (cs->exception_index == EXCP_SYSCALL) {
env->epcr += 4;
}
+ /* When we have an illegal instruction the error effective address
+ shall be set to the illegal instruction address. */
+ if (cs->exception_index == EXCP_ILLEGAL) {
+ env->eear = env->pc;
+ }
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
--
2.9.3
- [Qemu-devel] [PATCH 00/22] target/openrisc updates, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 01/22] target/openrisc: Rename the cpu from or32 to or1k, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 03/22] linux-user: Fix openrisc cpu_loop, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling status registers,
Richard Henderson <=
- [Qemu-devel] [PATCH 05/22] target/openrisc: Implement lwa, swa, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 06/22] target/openrisc: Tidy insn dumping, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 07/22] target/openrisc: Rationalize immediate extraction, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 08/22] target/openrisc: Streamline arithmetic and OVE, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 10/22] target/openrisc: Invert the decoding in dec_calc, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 12/22] target/openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 13/22] target/openrisc: Use movcond where appropriate, Richard Henderson, 2017/02/08
- [Qemu-devel] [PATCH 14/22] target/openrisc: Set flags on helpers, Richard Henderson, 2017/02/08