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[Qemu-devel] [PULL 00/12] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/12] target-arm queue |
Date: |
Fri, 10 Feb 2017 18:07:50 +0000 |
ARM queue: nothing particularly exciting here, but no
reason to sit on them for another week.
thanks
-- PMM
The following changes since commit 61eedf7aec0e2395aabd628cc055096909a3ea15:
tests/prom-env: Ease time-out problems on slow hosts (2017-02-10 15:44:53
+0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20170210
for you to fetch changes up to b4cc583f0285a2e1e78621dfba142f00ca47414a:
aspeed/smc: use a modulo to check segment limits (2017-02-10 17:40:30 +0000)
----------------------------------------------------------------
target-arm queue:
* aspeed: minor fixes
* virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI
* arm: enable basic TCG emulation of PMU for AArch64
----------------------------------------------------------------
Alexander Graf (4):
target-arm: Declare virtio-mmio as dma-coherent in dt
hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
hw/arm/virt: Declare fwcfg as dma cache coherent in dt
Cédric Le Goater (4):
aspeed: check for negative values returned by blk_getlength()
aspeed: remove useless comment on controller segment size
aspeed/smc: handle dummies only in fast read mode
aspeed/smc: use a modulo to check segment limits
Wei Huang (4):
target-arm: Add support for PMU register PMSELR_EL0
target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
target-arm: Add support for PMU register PMINTENSET_EL1
target-arm: Enable vPMU support under TCG mode
target/arm/cpu.h | 4 +--
hw/arm/aspeed.c | 22 +++++++++-----
hw/arm/vexpress.c | 1 +
hw/arm/virt-acpi-build.c | 2 ++
hw/arm/virt.c | 4 ++-
hw/ssi/aspeed_smc.c | 13 +++++----
target/arm/cpu.c | 2 +-
target/arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++------------
8 files changed, 88 insertions(+), 34 deletions(-)
- [Qemu-devel] [PULL 00/12] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength(), Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits, Peter Maydell, 2017/02/10