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[Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read m
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode |
Date: |
Fri, 10 Feb 2017 18:08:01 +0000 |
From: Cédric Le Goater <address@hidden>
HW works fine in normal read mode with dummy bytes being set. So let's
check this case to not transfer bytes.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/aspeed_smc.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 087b29e..7017707 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -536,10 +536,13 @@ static uint64_t aspeed_smc_flash_read(void *opaque,
hwaddr addr, unsigned size)
/*
* Use fake transfers to model dummy bytes. The value should
* be configured to some non-zero value in fast read mode and
- * zero in read mode.
+ * zero in read mode. But, as the HW allows inconsistent
+ * settings, let's check for fast read mode.
*/
- for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
- ssi_transfer(fl->controller->spi, 0xFF);
+ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
+ for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
+ ssi_transfer(fl->controller->spi, 0xFF);
+ }
}
for (i = 0; i < size; i++) {
--
2.7.4
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength(), Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode,
Peter Maydell <=
- [Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0, Peter Maydell, 2017/02/10
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/13